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    • 44. 发明申请
    • BURIED THERMALLY CONDUCTIVE LAYERS FOR HEAT EXTRACTION AND SHIELDING
    • 用于热提取和屏蔽的BURIED导热层
    • US20110309513A1
    • 2011-12-22
    • US12819022
    • 2010-06-18
    • David K. BiegelsenRaj B. Apte
    • David K. BiegelsenRaj B. Apte
    • H01L23/52H01L23/34H01L21/768
    • H01L23/3677H01L23/481H01L23/49822H01L2924/0002H01L2924/12044H01L2924/00
    • An embodiment is a method and apparatus for heat extraction and shielding in multi-block semiconductor devices. A plurality of blocks stacked on each other is interconnected by vertical vias filled with thermally conducting material and separated by buried thermally conductive layers. A thermally conductive layer is bonded to bottom or top of the plurality of blocks as a ground plane or a heat extraction layer. The thermally conductive layer has a high thermal conductivity.An embodiment is a method and apparatus for heat extraction and shielding in single-block semiconductor devices. A thermally insulative layer is deposited on a substrate. The thermally insulative layer is capable of supporting a thermal gradient to reduce heating of the substrate. A buried thermally conductive layer is formed inside the thermally insulative layer and has a vertical via to connect through the substrate to an external heat extracting layer. A semiconductor layer is deposited on the thermally insulative layer and patterned for electrical interconnects.
    • 一个实施例是用于多块半导体器件中的热提取和屏蔽的方法和装置。 彼此堆叠的多个块通过填充有导热材料并由埋入的导热层分隔的垂直通孔互连。 导热层结合到多个块的底部或顶部作为接地层或热提取层。 导热层具有高导热性。 一个实施例是用于单块半导体器件中的热提取和屏蔽的方法和装置。 绝热层沉积在基底上。 绝热层能够支持热梯度以减少基板的加热。 埋入导热层形成在绝热层的内部,并且具有垂直通孔,以将衬底连接到外部散热层。 半导体层沉积在绝热层上并对电互连构图。
    • 45. 发明申请
    • GATED CO-PLANAR POLY-SILICON THIN FILM DIODE
    • 嵌入式CO-PLANAR POLY-SILICON薄膜二极管
    • US20100181573A1
    • 2010-07-22
    • US12358171
    • 2009-01-22
    • JengPing LuRaj B. Apte
    • JengPing LuRaj B. Apte
    • H01L29/786H01L21/336
    • H01L29/66477H01L29/04H01L29/1604H01L29/20H01L29/66356H01L29/7391
    • A diode has a first contact of a material having a first conductivity type, a second contact of a material having a second conductivity type arranged co-planarly with the first contact, a channel arranged co-planarly between the first and second contacts, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A diode has a layer of material arranged on a substrate, a first region of material doped to have a first conductivity type, a second region of material doped to have a second conductivity type, a channel between the first and second regions formed of an undoped region, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A method includes forming a layer of material on a substrate, forming a first region of a first conductivity in the material, forming a second region of a second conductivity in the material, arranged so as to provide a channel region between the first and second regions, the channel region remaining undoped, depositing a layer of gate dielectric on the layer of material, arranging a gate adjacent the channel region on the gate dielectric, and electrically connecting a voltage source to the gate.
    • 二极管具有第一导电类型的材料的第一接触,与第一接触面共面布置的具有第二导电类型的材料的第二接触,在第一和第二接触之间共面布置的沟道,栅极 布置在所述通道附近,以及电连接到所述栅极的电压源。 二极管具有布置在衬底上的材料层,第一掺杂材料区域具有第一导电类型,掺杂第二导电类型的第二材料区域,由未掺杂的第一和第二区域形成的沟道 区域,邻近沟道布置的栅极和电连接到栅极的电压源。 一种方法包括在衬底上形成材料层,在材料中形成第一导电性的第一区域,在材料中形成第二导电性的第二区域,其布置成在第一和第二区域之间提供沟道区域 ,沟道区域保留未掺杂,在该材料层上沉积一层栅极电介质,在栅极电介质上布置与该沟道区相邻的栅极,以及将电压源电连接至该栅极。
    • 46. 发明授权
    • Low noise charge gain hybrid imager
    • 低噪声电荷增益混合成像仪
    • US07623169B2
    • 2009-11-24
    • US10431255
    • 2003-05-07
    • Raj B. Apte
    • Raj B. Apte
    • H04N3/14H04N5/335H01L27/00
    • H01L27/14634H04N5/374H04N5/378
    • In one aspect of the present application, provided is a charge gain imaging system and a method of operating the charge gain imaging system. The method includes collecting a pixel charge. The collected pixel charge being stored by a pixel capacitance (Cp). Thereafter the pixel having the stored pixel charge is selected via a pixel select switch, and the pixel voltage is transferred and stored by data line capacitance (Cd) of a data line of the imager. An amplifier select switch is activated connecting the data line to a charge amplifier, and a charge gain defined by a relationship Cd/Cp, is sensed by a charge amplifier.
    • 在本申请的一个方面中,提供了一种电荷增益成像系统和操作电荷增益成像系统的方法。 该方法包括收集像素电荷。 所收集的像素电荷由像素电容(Cp)存储。 此后,通过像素选择开关选择具有存储的像素电荷的像素,并且通过成像器的数据线的数据线电容(Cd)传送和存储像素电压。 激活了将数据线连接到电荷放大器的放大器选择开关,并且通过电荷放大器感测由关系Cd / Cp定义的电荷增益。
    • 47. 发明申请
    • METHOD AND SYSTEM FOR IMPROVED TESTING OF TRANSISTOR ARRAYS
    • 用于改进晶体管阵列测试的方法和系统
    • US20090219035A1
    • 2009-09-03
    • US12040807
    • 2008-02-29
    • Raj B. Apte
    • Raj B. Apte
    • H01H31/02
    • G09G3/006
    • An electronic test system to evaluate the pixel and array properties of active-matrix displays that use charge or current sensitive circuits attached to the array data lines is described. Leakage-current, charging time, and other metrics can be measured for all pixels in the array without electrical or optical connection to the interior of the array. In accordance with the presently described embodiments, charge or current sensitive amplifiers and selected voltage drivers may be used in conjunction with variable timing and voltages to determine individual transistor properties over an entire array in just a few seconds. Signals to be measured may be injected in several ways: first, a capacitive elastomer laminate (or plate) may be applied to the surface of the array, making a capacitance with the pixel pad; second, gate lines may be used to inject charge into pixels that connect to more than one gate line; third, digital or analog drivers connected to the data lines may be used to charge the pixel to varying states; fourth, the dc-bias level of the charge or current sensitive readout electronics may be shifted relative to the gate voltages to charge the pixel. Connection in the system between components is achieved through flex connectors or other appropriate means. Ultimately, an output signal for each pixel is measured. Thus, based on the output signal, the charging time or current, the leakage time or current, and other pixel or transistor parameters may be characterized for the entire array.
    • 描述了一种用于评估使用附加到阵列数据线的电荷或电流敏感电路的有源矩阵显示器的像素和阵列特性的电子测试系统。 对于阵列中的所有像素,可以测量漏电流,充电时间和其他度量,而无需连接到阵列内部的电或光连接。 根据目前描述的实施例,电荷或电流敏感放大器和所选择的电压驱动器可以结合可变定时和电压使用,以在短短几秒内在整个阵列上确定单个晶体管属性。 要测量的信号可以以几种方式注入:首先,可以将电容弹性体层压板(或板)施加到阵列的表面,从而与像素焊盘形成电容; 第二,可以使用栅极线将电荷注入到连接到多于一条栅极线的像素中; 第三,连接到数据线的数字或模拟驱动器可以用于将像素充电到变化的状态; 第四,电荷或电流敏感读出电路的直流偏置电平可以相对于栅极电压移位,以对像素充电。 通过柔性连接器或其他适当的方法实现组件之间的系统连接。 最终,测量每个像素的输出信号。 因此,基于输出信号,可以对整个阵列表征充电时间或电流,泄漏时间或电流以及其它像素或晶体管参数。