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    • 42. 发明公开
    • HYBRID R-2R STRUCTURE FOR LOW GLITCH NOISE SEGMENTED DAC
    • 杂交R-2R STRUKTURFÜRSEGMENTIGTEN数字模拟服务器MIT GERINGEMSTÖRIMPULSRAUSCHEN
    • EP3149858A1
    • 2017-04-05
    • EP15722019.5
    • 2015-05-06
    • Qualcomm Incorporated
    • LEE, Sang MinSEO, Dongwon
    • H03M1/06H03M1/08H03M1/68H03M1/78
    • H03M1/0863H03M1/0612H03M1/0881H03M1/687H03M1/785
    • The apparatus may be an N-bit DAC including (2M-1) parallel stages associated with M most significant bits, and (N-M) stages associated with (N-M) least significant bits. The (2M-1) parallel stages may deliver a first current to current-summing nodes of the DAC. The (N-M) stages may include a resistive network and a second pair of switches, and may deliver a second current to the resistive network of the stage. Each resistive network may scale the respectively delivered currents according to a binary weight of a stage corresponding to the resistive network, and may deliver the scaled currents to the pair of current-summing nodes. At least one of the (N-M) stages may be separated from the remaining stages.
    • 该装置可以是包括与M个最高有效位相关联的(2M-1)并行级的N位DAC和与(N-M)个最低有效位相关联的(N-M)级。 (2M-1)并联级可以将第一电流传送到DAC的电流求和节点。 (N-M)级可以包括电阻网络和第二对开关,并且可以将第二电流传递到级的电阻网络。 每个电阻网络可以根据与电阻网络相对应的级的二进制权重对分别递送的电流进行缩放,并且可以将缩放的电流传送到一对电流求和节点。 (N-M)级中的至少一个可以与其余级分离。