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41. 发明授权

US10534608B2 Local computation logic embedded in a register file to accelerate programs 有权
公开(公告)号：US10534608B2
公开(公告)日：2020-01-14
申请号：US13211701
申请日：2011-08-17
申请人： Pradip Bose , Alper Buyuktosunoglu , Jeffrey Haskell Derby , Michele Martino Franceschini , Robert Kevin Montoye , Augusto J. Vega
发明人： Pradip Bose , Alper Buyuktosunoglu , Jeffrey Haskell Derby , Michele Martino Franceschini , Robert Kevin Montoye , Augusto J. Vega
IPC分类号： G06F15/78 , G06F15/16 , G06F9/30 , G06F9/38
摘要： A central processing unit system includes: a pipeline configured to receive an instruction; and a register file partitioned into one or more subarrays where (i) the register file includes one or more computation elements and (ii) the one or more computation elements are directly connected to one or more subarrays.

42. 发明授权

US08914764B2 Adaptive workload based optimizations coupled with a heterogeneous current-aware baseline design to mitigate current delivery limitations in integrated circuits 有权
标题翻译：基于自适应工作负载的优化与异构电流感知基线设计相结合，以减轻集成电路中的当前传输限制
公开(公告)号：US08914764B2
公开(公告)日：2014-12-16
申请号：US13526252
申请日：2012-06-18
申请人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
发明人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5072 , G06F17/5036
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译：与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。设计辅助工具用于根据当前的交付要求在整个芯片上分配C4。该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。

43. 发明授权

US08639955B2 Method and system for controlling power in a chip through a power performance monitor and control unit 有权
标题翻译：通过功率性能监测和控制单元控制芯片功率的方法和系统
公开(公告)号：US08639955B2
公开(公告)日：2014-01-28
申请号：US13292712
申请日：2011-11-09
申请人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Prabhakar N. Kudva
发明人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Prabhakar N. Kudva
IPC分类号： G06F1/00
CPC分类号： G06F1/206 , G06F1/3203 , Y02D10/16
摘要： A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要翻译：用于控制微处理器系统中的功率和性能的系统和方法包括集成到微处理器系统中的监视和控制系统。监视和控制系统包括具有多个层的层次结构。层次结构中的每层都响应来自更高级别的命令，并且命令提供关于操作和功率分配的指令，使得较高级别提供操作模式和预算以降低级别，并且较低级别向较高级别提供反馈在全球和本地控制和管理微处理器系统中的电力使用。

44. 发明授权

US08458501B2 Measuring data switching activity in a microprocessor 失效
标题翻译：测量微处理器中的数据交换活动
公开(公告)号：US08458501B2
公开(公告)日：2013-06-04
申请号：US12844372
申请日：2010-07-27
申请人： Pradip Bose , Alper Buyuktosunoglu , Christopher J. Gonzalez , Moinuddin K. Qureshi , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Christopher J. Gonzalez , Moinuddin K. Qureshi , Victor Zyuban
IPC分类号： G06F1/32 , G06F3/00
CPC分类号： G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126
摘要： A mechanism is provided for approximating data switching activity in a data processing system. A data switching activity identification mechanism in the data processing system receives an identification of a set of data storage devices and a set of bits in the set of data storage devices in the data processing system to be monitored for the data switching activity. The data switching activity identification mechanism sums a count of the identified bits that have changed state for the data storage device along with other counts of the identified bits that have changed state for other data storage devices in the set of data storage devices to form an approximation of data switching activity. A power manager in the data processing system then adjusts a set of operational parameters associated with the data processing system using the approximation of data switching activity.
摘要翻译：提供了一种用于近似数据处理系统中的数据交换活动的机制。数据处理系统中的数据交换活动识别机制在数据处理系统中接收数据存储设备的集合的标识和数据存储设备中的一组位，以对数据交换活动进行监控。数据交换活动识别机制对数据存储装置的已改变状态的已识别比特的计数与数据存储装置中的其他数据存储装置的已改变状态的识别比特的其他计数相加以形成近似值的数据交换活动。数据处理系统中的电源管理器然后使用数据交换活动的近似来调整与数据处理系统相关联的一组操作参数。

45. 发明申请

US20120260117A1 Dynamically Tune Power Proxy Architectures 有权
标题翻译：动态调谐电源代理架构
公开(公告)号：US20120260117A1
公开(公告)日：2012-10-11
申请号：US13079842
申请日：2011-04-05
申请人： Emrah Acar , Pradip Bose , Bishop C. Brock , Alper Buyuktosunoglu , Michael S. Floyd , Maria L. Pesantez , Gregory S. Still
发明人： Emrah Acar , Pradip Bose , Bishop C. Brock , Alper Buyuktosunoglu , Michael S. Floyd , Maria L. Pesantez , Gregory S. Still
IPC分类号： G06F1/28
CPC分类号： G06F1/3243 , Y02D10/152
摘要： A mechanism is provided for automatically tuning power proxy architectures. Based on the set of conditions related to an application being executed on a microprocessor core, a weight factor to use for each activity in a set of activities being monitored for the microprocessor core is identified, thereby forming a set of weight factors. A power usage estimate value is generated using the set of activities and the set of weight factors. A determination is made as to whether the power usage estimate value is greater than a power proxy threshold value identifying a maximum power usage for the microprocessor core. Responsive to the power usage estimate value being greater than the power proxy threshold value, a set of signals is sent to one or more on-chip actuators in the power proxy unit associated with the microprocessor core and a set of operational parameters associated with the component are adjusted.
摘要翻译：提供了一种自动调整电源代理架构的机制。基于与在微处理器核心上执行的应用有关的一组条件，识别用于针对微处理器核心的一组活动中的每个活动的权重因子，从而形成一组权重因子。使用一组活动和一组权重因子生成用电量估计值。确定功率使用估计值是否大于识别微处理器核的最大功率使用的功率代理阈值。响应于功率使用估计值大于功率代理阈值，一组信号被发送到与微处理器核心相关联的功率代理单元中的一个或多个片上致动器，以及与该组件相关联的一组操作参数被调整。

46. 发明申请

US20120119717A1 Voltage Regulator Module with Power Gating and Bypass 失效
标题翻译：具有电源门控和旁路的稳压器模块
公开(公告)号：US20120119717A1
公开(公告)日：2012-05-17
申请号：US12944392
申请日：2010-11-11
申请人： Pradip Bose , Alper Buyuktosunoglu , Hans M. Jocobson , Seongwon Kim
发明人： Pradip Bose , Alper Buyuktosunoglu , Hans M. Jocobson , Seongwon Kim
IPC分类号： G05F1/10
CPC分类号： G05F1/575 , G05F1/565
摘要： Mechanisms are provided for either power gating or bypassing a voltage regulator. Responsive to receiving an asserted power gate signal to power gate the output voltage of the voltage regulator, at least one of first control circuitry power gates the output voltage of a first circuit or second control circuitry power gates the output voltage of a second circuit such that substantially no voltage to is output by the first circuit to a primary output node. Responsive to receiving an asserted bypass signal to bypass the output voltage of the voltage regulator, at least one of the first control circuitry bypasses the output voltage of the first circuit or the second control circuitry bypasses the output voltage of a second circuit such that substantially the voltage of a voltage source is output by the first circuit to the primary output node.
摘要翻译：提供电源门控或旁路电压调节器的机制。响应于接收到被断言的电源门信号以对所述电压调节器的输出电压进行电源门控，第一控制电路电源的至少一个功率门是第一电路或第二控制电路电路的输出电压门控第二电路的输出电压，使得基本上没有电压被第一电路输出到主输出节点。响应于接收断言的旁路信号以绕过电压调节器的输出电压，第一控制电路中的至少一个旁路第一电路或第二控制电路的输出电压旁路第二电路的输出电压，使得基本上电压源的电压由第一电路输出到主输出节点。

47. 发明授权

US08112642B2 Method and system for controlling power in a chip through a power-performance monitor and control unit 失效
标题翻译：通过功率监控和控制单元控制芯片功率的方法和系统
公开(公告)号：US08112642B2
公开(公告)日：2012-02-07
申请号：US12132044
申请日：2008-06-03
申请人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Prabhakar N. Kudva
发明人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Prabhakar N. Kudva
IPC分类号： G06F1/00 , G06F1/26
CPC分类号： G06F1/206 , G06F1/3203 , Y02D10/16
摘要： A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要翻译：用于控制微处理器系统中的功率和性能的系统和方法包括集成到微处理器系统中的监视和控制系统。监视和控制系统包括具有多个层的层次结构。层次结构中的每层都响应来自更高级别的命令，并且命令提供关于操作和功率分配的指令，使得较高级别提供操作模式和预算以降低级别，并且较低级别向较高级别提供反馈在全球和本地控制和管理微处理器系统中的电力使用。

48. 发明申请

US20080256345A1 Method and Apparatus for Conserving Power by Throttling Instruction Fetching When a Processor Encounters Low Confidence Branches in an Information Handling System 失效
标题翻译：当处理器在信息处理系统中遇到低置信度时通过调节指令获取来节省电力的方法和装置
公开(公告)号：US20080256345A1
公开(公告)日：2008-10-16
申请号：US11733589
申请日：2007-04-10
申请人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Michael Karl Gschwind , Ravi Nair , Robert Alan Philhower , Wolfram Sauer , Raymond Cheung Yeung
发明人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Michael Karl Gschwind , Ravi Nair , Robert Alan Philhower , Wolfram Sauer , Raymond Cheung Yeung
IPC分类号： G06F7/38
CPC分类号： G06F9/3844 , G06F1/3203 , G06F9/3802 , G06F9/3806
摘要： An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions.
摘要翻译：一种信息处理系统包括处理器，每当对分支指令队列中存储的分支指令的分支预测中的不准确性或缺乏置信度的不准确性或缺乏置信度超过预定的不准确度或误差的阈值置信水平时，可以节制指令获取器。以这种方式，当处理器可能会错误地预测分支指令的结果时，获取操作减慢以节省处理器功率。当处理器可能正确预测分支指令的结果时，获取操作将返回全速。

49. 发明申请

US20050083081A1 Method and structure for short range leakage control in pipelined circuits 失效
公开(公告)号：US20050083081A1
公开(公告)日：2005-04-21
申请号：US10685863
申请日：2003-10-15
申请人： Hans Jacobson , Pradip Bose , Alper Buyuktosunoglu , Peter Cook , Philip Emma , Prabhakar Kudva , Stanley Schuster
发明人： Hans Jacobson , Pradip Bose , Alper Buyuktosunoglu , Peter Cook , Philip Emma , Prabhakar Kudva , Stanley Schuster
IPC分类号： H03K5/00 , H03K17/16 , H03K19/00
CPC分类号： H03K19/0016
摘要： Leakage current control devices include a circuit having one or more functions in a data path where the functions are executed in a sequence. Each of the functions has power reduction logic to energize each respective function. A leakage control circuit interacts with the power reduction logic, so that the functions are energized or deenergized in a control sequence such that the functions where the data is resident are energized and at least one of the other functions is not energized.

50. 发明授权

US09043626B2 Power shifting in multicore platforms by varying SMT levels 有权
标题翻译：通过改变SMT级别在多核平台中进行功率转换
公开(公告)号：US09043626B2
公开(公告)日：2015-05-26
申请号：US13529161
申请日：2012-06-21
申请人： Pradip Bose , Alper Buyuktosunoglu , Dilma Menezes Da Silva , Hubertus Franke , Priyanka Tembey
发明人： Pradip Bose , Alper Buyuktosunoglu , Dilma Menezes Da Silva , Hubertus Franke , Priyanka Tembey
IPC分类号： G06F1/32 , G06F9/50
CPC分类号： G06F1/3206 , G06F1/26 , G06F1/3203 , G06F1/329 , G06F9/4893 , G06F9/50 , Y02D10/24
摘要： Power consumption in a microprocessor platform is managed by setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications. The multi-core microprocessor platform contains a plurality of physical cores, and each physical core is configurable into a plurality of logical cores. A simultaneous multithreading level in at least one physical core is adjusted by changing the number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level. Performance and power data based on simultaneous multi-threading levels are used in selecting the physical core to be adjusted.
摘要翻译：通过设置执行多线程应用程序的多核微处理器平台消耗的功耗的峰值功率级别来管理微处理器平台中的功耗。多核微处理器平台包含多个物理核，每个物理核可配置成多个逻辑核。响应于多核微处理器平台的功率消耗水平超过峰值功率水平，通过改变该物理核心上的逻辑核心数来调整至少一个物理核心中的同时多线程级别。基于同步多线程级别的性能和功耗数据用于选择要调整的物理内核。

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