专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US07718480B1 ESD clamps and NMOS arrays with increased electrical overstress robustness 有权
标题翻译： ESD钳位和NMOS阵列具有增加的电应力坚固性
公开(公告)号：US07718480B1
公开(公告)日：2010-05-18
申请号：US11138221
申请日：2005-05-26
申请人： Vladislav Vashchenko , Marcel ter Book , Peter J. Hopper
发明人： Vladislav Vashchenko , Marcel ter Book , Peter J. Hopper
IPC分类号： H01L21/00
CPC分类号： H01L27/0266 , H01L29/0692 , H01L29/1045 , H01L29/1087 , H01L29/78
摘要： In an NMOS active clamp device and an NMOS active clamp array with multiple source and drain contacts, the robustness against ESD events is increased by reducing channel resistance through the inclusion of one or more p+ regions formed at least partially in the source and electrically connected to the one or more source contacts.
摘要翻译：在具有多个源极和漏极触点的NMOS有源钳位装置和NMOS有源钳位阵列中，通过包括至少部分地形成在源极中的一个或多个p +区域并且电连接到一个或多个源接触。

42. 发明授权

US07639464B1 High holding voltage dual direction ESD clamp 有权
标题翻译：高保持电压双向ESD钳位
公开(公告)号：US07639464B1
公开(公告)日：2009-12-29
申请号：US11376492
申请日：2006-03-15
申请人： Vladislav Vashchenko , Peter J. Hopper
发明人： Vladislav Vashchenko , Peter J. Hopper
IPC分类号： H02H9/00 , H02H3/20
CPC分类号： H01L27/0266
摘要： In a dual direction ESD protection structure, first and second NMOS devices are serially connected back-to-back by connecting their drains or their sources using a common floating interconnect, while ensuring that the devices remain isolated from each other.
摘要翻译：在双向ESD保护结构中，第一和第二NMOS器件通过使用公共浮动互连连接它们的漏极或其源极而被背对背地串联连接，同时确保器件保持彼此隔离。

43. 发明授权

US07635614B1 Double gate NLDMOS SCR device with controllable switching characteristics 有权
标题翻译：双门NLDMOS SCR器件具有可控开关特性
公开(公告)号：US07635614B1
公开(公告)日：2009-12-22
申请号：US11724622
申请日：2007-03-15
申请人： Vladimir Kuznetsov , Vladislav Vashchenko , Peter J. Hopper
发明人： Vladimir Kuznetsov , Vladislav Vashchenko , Peter J. Hopper
IPC分类号： H01L21/323 , H01L29/74
CPC分类号： H01L29/7436 , H01L29/7404 , H01L29/749
摘要： An NLDMOS SCR device based on an LDMOS fabrication process includes a dual gate to provide controllable switching characteristics to allow it to be used for ESD protection of fast switching voltage regulators.
摘要翻译：基于LDMOS制造工艺的NLDMOS SCR器件包括提供可控开关特性以允许其用于快速开关电压调节器的ESD保护的双栅极。

44. 发明申请

US20090162978A1 Method of Forming a SiGe DIAC ESD Protection Structure 有权
标题翻译：形成SiGe DIAC ESD保护结构的方法
公开(公告)号：US20090162978A1
公开(公告)日：2009-06-25
申请号：US12395506
申请日：2009-02-27
申请人： Vladislav Vashchenko , Peter J. Hopper
发明人： Vladislav Vashchenko , Peter J. Hopper
IPC分类号： H01L21/332
CPC分类号： H01L27/0259
摘要： A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of the SiGe transistors.
摘要翻译：用于交流（DIAC）静电放电（ESD）保护电路的二极管形成在利用非常薄的集电极区域的硅锗（SiGe）合金双极晶体管（HBT）工艺中。通过利用SiGe晶体管的基极结构和发射极结构，提供一对待保护焊盘的ESD保护。

45. 发明授权

US07075341B1 Low area linear time-driver circuit 有权
标题翻译：低面积线性时间驱动电路
公开(公告)号：US07075341B1
公开(公告)日：2006-07-11
申请号：US10823455
申请日：2004-04-13
申请人： Vladislav Vashchenko , Yuri Mirgorodski , Peter J. Hopper
发明人： Vladislav Vashchenko , Yuri Mirgorodski , Peter J. Hopper
IPC分类号： H03B1/00
CPC分类号： H01L27/0266
摘要： A linear time-driver circuit is provided that consumes low space on-chip. The time-driver circuit is based upon the small capacitor charge of the merged region of a 5V tolerant cascaded NMOS device, a single gate device and a zener diode.
摘要翻译：提供消耗片上低空间的线性时间驱动电路。时间驱动电路基于5V容限级联NMOS器件，单栅极器件和齐纳二极管的合并区域的小电容器电荷。

46. 发明授权

US06964907B1 Method of etching a lateral trench under an extrinsic base and improved bipolar transistor 有权
标题翻译：在外部基极和改进的双极晶体管之下蚀刻横向沟槽的方法
公开(公告)号：US06964907B1
公开(公告)日：2005-11-15
申请号：US10716276
申请日：2003-11-17
申请人： Peter J. Hopper , Alexei Sadovnikov , Vladislav Vashchenko , Peter Johnson
发明人： Peter J. Hopper , Alexei Sadovnikov , Vladislav Vashchenko , Peter Johnson
IPC分类号： H01L21/302 , H01L21/306 , H01L21/331 , H01L29/04 , H01L29/08 , H01L29/10 , H01L29/732
CPC分类号： H01L21/30608 , H01L29/045 , H01L29/0649 , H01L29/0821 , H01L29/1004 , H01L29/66272 , H01L29/7322
摘要： In a BJT, the extrinsic base to collector capacitance is reduced by forming a lateral trench between the extrinsic base region and collector. This is typically done by using an anisotropic wet etch process in a direction of a orientation wafer.
摘要翻译：在BJT中，通过在外部基极区域和集电极之间形成横向沟槽来减小外部基极到集电极电容。这通常通过使用<100>取向晶片的<110>方向的各向异性湿蚀刻工艺来完成。

47. 发明授权

US06956269B1 Spin-polarization of carriers in semiconductor materials for spin-based microelectronic devices 有权
标题翻译：用于自旋基微电子器件的半导体材料中载流子的自旋极化
公开(公告)号：US06956269B1
公开(公告)日：2005-10-18
申请号：US10744252
申请日：2003-12-22
申请人： Vladislav Vashchenko , Michael Mian , Peter J. Hopper
发明人： Vladislav Vashchenko , Michael Mian , Peter J. Hopper
IPC分类号： H01L29/66 , H01L29/82
CPC分类号： H01L29/66984
摘要： Spin-based microelectronic devices can be realized by utilizing spin-polarized ferromagnetic materials positioned near, or embedded in, a semiconductor channel of a microelectronic device. Applying an electric field across the channel can cause carriers flowing through the channel to deviate toward one of the ferromagnetic materials, such that the spin of the carriers tends to align with the spin polarization of the respective material. Such a process allows for the controlled spin-polarization of carriers in a semiconductor channel, and hence the development of spin-based microelectronics, without having to inject spin-polarized carriers from a ferromagnet into a semiconductor channel. Such a process avoids the Schottky barrier problem plaguing existing approaches to spin-based microelectronics, while allowing the devices to be based on silicon substrates that are well-known and used in the industry.
摘要翻译：旋转微电子器件可以通过利用位于微电子器件的半导体通道附近或嵌入其中的自旋极化铁磁材料来实现。通过通道施加电场可以使流过通道的载流子偏向铁磁材料之一，使得载流子的自旋倾向于与相应材料的自旋极化对准。这种方法允许半导体通道中载流子的受控自旋极化，从而允许自旋基微电子学的发展，而不必将自旋极化载流子从铁磁体注入到半导体通道中。这种过程避免了肖特基势垒问题困扰着现有的基于旋转微电子学的方法，同时允许器件基于业界众所周知和使用的硅衬底。

48. 发明授权

US06906357B1 Electrostatic discharge (ESD) protection structure with symmetrical positive and negative ESD protection 有权
标题翻译：静电放电（ESD）保护结构具有对称的正负极ESD保护
公开(公告)号：US06906357B1
公开(公告)日：2005-06-14
申请号：US10683625
申请日：2003-10-10
申请人： Vladislav Vashchenko , Marcel ter Beek , Peter J. Hopper , Ann Concannon
发明人： Vladislav Vashchenko , Marcel ter Beek , Peter J. Hopper , Ann Concannon
IPC分类号： H01L27/02 , H01L29/72
CPC分类号： H01L27/0259
摘要： An apparatus including an electrostatic discharge (ESD) protection structure with a diac in which substancially similar ESD protection is provided for both positive and negative ESD voltages appearing at the circuit electrode sought to be protected.
摘要翻译：一种包括具有diac的静电放电（ESD）保护结构的装置，其中为保护电路电极处出现的正和负ESD电压提供了基本相似的ESD保护。

49. 发明授权

US06903979B1 Efficient method of PMOS stacked-gate memory cell programming utilizing feedback control of substrate current 有权
标题翻译：利用衬底电流的反馈控制的PMOS堆叠栅极存储器单元编程的有效方法
公开(公告)号：US06903979B1
公开(公告)日：2005-06-07
申请号：US10664758
申请日：2003-09-17
申请人： Yuri Mirgorodski , Vladislav Vashchenko , Peter J. Hopper , Douglas J. Brisbin
发明人： Yuri Mirgorodski , Vladislav Vashchenko , Peter J. Hopper , Douglas J. Brisbin
IPC分类号： G11C16/00 , G11C16/10
CPC分类号： G11C16/10
摘要： A method of programming a PMOS stacked gate memory cell is provided that utilizes the correlation between injection current and substrate current during the programming cycle to provide a feedback correction to the control gate of the memory cell to compensate for the negative potential shift on the floating gate as a result of its charging time.
摘要翻译：提供了一种编程PMOS堆叠栅极存储单元的方法，其利用在编程周期期间的注入电流和衬底电流之间的相关性来向存储器单元的控制栅极提供反馈校正，以补偿浮置栅极上的负电位移位作为其充电时间的结果。

50. 发明授权

US06822294B1 High holding voltage LVTSCR 有权
标题翻译：高保持电压LVTSCR
公开(公告)号：US06822294B1
公开(公告)日：2004-11-23
申请号：US09896681
申请日：2001-06-29
申请人： Vladislav Vashchenko , Ann Concannon , Peter J. Hopper
发明人： Vladislav Vashchenko , Ann Concannon , Peter J. Hopper
IPC分类号： H01L2362
CPC分类号： H01L27/0262 , H01L29/87
摘要： In an ESD protection device using a LVTSCR-like structure, the holding voltage is increased by placing the p+ emitter outside the drain of the device, thereby retarding the injection of holes from the p+ emitter. The p+ emitter may be implemented in one or more emitter regions formed outside the drain. The drain is split between a n+ drain and a floating n+ region near the gate to avoid excessive avalanche injection and resultant local overheating.
摘要翻译：在使用类似LVTSCR的结构的ESD保护器件中，通过将p +发射极放置在器件的漏极之外，从而延长了p +发射极的空穴注入，从而提高了保持电压。 p +发射极可以在形成在漏极外部的一个或多个发射极区域中实现。漏极在栅极附近的n +漏极和浮动n +区域之间分开，以避免过度的雪崩注入和局部过热。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式