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41. 发明申请

US20070278541A1 Spacer engineering on CMOS devices 审中-公开
标题翻译： CMOS器件上的间隔工程
公开(公告)号：US20070278541A1
公开(公告)日：2007-12-06
申请号：US11446912
申请日：2006-06-05
申请人： Chien-Chao Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Fu-Liang Yang
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/1083 , H01L29/6656 , H01L29/7842
摘要： A MOS device having a reduced LDD dopant diffusion length and a method for forming the same are provided. The MOS device includes a gate stack over a semiconductor substrate, a spacer liner on a sidewall of the gate stack and having a portion over the semiconductor substrate, and a spacer over the spacer liner. The spacer for a PMOS device preferably has a tensile stress, and the spacer for an NMOS device preferably has a compressive stress.
摘要翻译：提供具有降低的LDD掺杂剂扩散长度的MOS器件及其形成方法。 MOS器件包括在半导体衬底上的栅极堆叠，在栅极堆叠的侧壁上的间隔衬垫，并且具有半导体衬底上的部分，以及间隔衬垫上的间隔物。用于PMOS器件的间隔物优选具有拉伸应力，并且用于NMOS器件的间隔物优选地具有压应力。

42. 发明申请

US20070222035A1 Stress intermedium engineering 审中-公开
标题翻译：应力中介工程
公开(公告)号：US20070222035A1
公开(公告)日：2007-09-27
申请号：US11387601
申请日：2006-03-23
申请人： Chien-Chao Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Fu-Liang Yang
IPC分类号： H01L29/06
CPC分类号： H01L29/78 , H01L29/7843 , H01L29/7845
摘要： Embodiments of the invention provide structures and methods for forming a strained MOS transistor. A stressor layer is formed over the transistor. Embodiments include an intermedium layer between the stressor layer and a portion of the transistor. In an embodiment, the intermedium comprises a layer formed between the stressor layer and the gate electrode sidewall spacers. In another embodiment, the intermedium comprises a silicided portion of the substrate formed over the LDS/LDD regions. A transistor that includes the intermedium and, stressor layer has a vertically oriented stress within the channel region. The vertically oriented stress is tensile in a PMOS transistor and compressive in an NMOS transistor.
摘要翻译：本发明的实施例提供了用于形成应变MOS晶体管的结构和方法。在晶体管上方形成应力层。实施例包括应力层与晶体管的一部分之间的中间层。在一个实施例中，中间层包括在应力层和栅电极侧壁间隔件之间形成的层。在另一个实施例中，中间层包括在LDS / LDD区上形成的衬底的硅化物部分。包括中间层和应力层的晶体管在沟道区域内具有垂直取向的应力。垂直取向的应力是PMOS晶体管中的拉伸和NMOS晶体管中的压缩。

43. 发明授权

US07265425B2 Semiconductor device employing an extension spacer and a method of forming the same 有权
标题翻译：采用延伸间隔物的半导体装置及其形成方法
公开(公告)号：US07265425B2
公开(公告)日：2007-09-04
申请号：US10989073
申请日：2004-11-15
申请人： Kuang-Hsin Chen , Tang-Xuan Zhong , Chien-Chao Huang , Cheng-Kuo Wen , Di-Hong Lee
发明人： Kuang-Hsin Chen , Tang-Xuan Zhong , Chien-Chao Huang , Cheng-Kuo Wen , Di-Hong Lee
IPC分类号： H01L29/94
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/76829 , H01L29/51 , H01L29/6656 , H01L29/66575 , H01L29/7833 , H01L29/7843
摘要： A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.
摘要翻译：形成在半导体衬底上的半导体器件及其形成方法。在一个实施例中，半导体器件包括半导体衬底上的栅极和栅极侧壁上的电介质衬垫。该半导体器件还包括一个与半导体衬底相邻且沿着绝缘衬垫横向延伸延伸的间隔件。半导体器件还包括位于半导体衬底的上表面下方并与栅极下方的沟道区相邻的源极/漏极。源极/漏极延伸在电介质衬垫和延伸垫片下面。半导体器件还包括在源极/漏极的一部分上方的硅化物区域，并且沿着半导体衬底横向延伸超过延伸间隔物。因此，延伸间隔物介于电介质衬垫和位于源极/漏极的一部分之上的硅化物区域之间。

44. 发明授权

US07183137B2 Method for dicing semiconductor wafers 有权
标题翻译：切割半导体晶片的方法
公开(公告)号：US07183137B2
公开(公告)日：2007-02-27
申请号：US10725697
申请日：2003-12-01
申请人： Hsin-Hui Lee , Chien-Chao Huang , Chao-Hsiung Wang , Fu-Liang Yang , Chenming Hu
发明人： Hsin-Hui Lee , Chien-Chao Huang , Chao-Hsiung Wang , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/50 , H01L21/78
CPC分类号： H01L21/78 , B28D5/00
摘要： A method is disclosed for dicing a wafer having a base material with a diamond structure. The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side. The wafer is then diced through at least one line along a direction at a predetermined offset angle from a natural cleavage direction of the diamond structure.
摘要翻译：公开了一种用于切割具有金刚石结构的基底材料的晶片的方法。晶片首先进行抛光处理，其中将晶片的预定部分从其背面抛光。然后将晶片沿着与金刚石结构的天然裂解方向成预定偏移角的方向通过至少一条线切割。

45. 发明申请

US20060202237A1 Metal gate semiconductor device and manufacturing method 有权
标题翻译：金属栅极半导体器件及其制造方法
公开(公告)号：US20060202237A1
公开(公告)日：2006-09-14
申请号：US11400853
申请日：2006-04-10
申请人： Chien-Chao Huang , Kuang-Hsin Chen , Fu-Liang Yang
发明人： Chien-Chao Huang , Kuang-Hsin Chen , Fu-Liang Yang
IPC分类号： H01L29/768
CPC分类号： H01L29/66553 , H01L21/28097 , H01L21/82345 , H01L21/823468 , H01L29/665 , H01L29/66507 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first layer. The layers are etched to form a plurality of adjacent spacers, including a first spacer located on the substrate and adjacent the gate electrode and a second spacer adjacent the first spacer. The first spacer is then etched and a metal layer is formed on the device immediately adjacent to the gate electrode. The metal layer is then reacted with the gate electrode to form a metal gate.
摘要翻译：一种用于制造金属栅极的方法包括提供包括位于基板上的栅电极的基板。形成多个层，包括位于衬底上的第一层和栅电极以及与第一层相邻的第二层。这些层被蚀刻以形成多个相邻的间隔物，包括位于衬底上并且邻近栅电极的第一间隔物和邻近第一间隔物的第二间隔物。然后蚀刻第一间隔物，并且在紧邻栅电极的器件上形成金属层。然后金属层与栅电极反应形成金属栅极。

46. 发明申请

US20060138557A1 Novel CMOS device 审中-公开
标题翻译：新型CMOS器件
公开(公告)号：US20060138557A1
公开(公告)日：2006-06-29
申请号：US11356865
申请日：2006-02-17
申请人： Chien-Chao Huang , Chao-Hsing Wang , Chung-Hu Ge , Chenming Hu
发明人： Chien-Chao Huang , Chao-Hsing Wang , Chung-Hu Ge , Chenming Hu
IPC分类号： H01L29/76
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823828
摘要： A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.
摘要翻译：一种方法，包括提供具有邻近PMOS器件的NMOS器件的衬底，并在所述NMOS和PMOS器件上形成第一应力层，其中所述第一应力层包括第一拉伸应力层或压缩应力层。在第一应力层上形成蚀刻停止层，并且从NMOS器件上去除第一应力层和蚀刻停止层的部分，留下PMOS器件上的第一应力层和蚀刻停止层。第二拉伸应力层形成在NMOS器件上并且在第一应力层和蚀刻停止层上方，并且第二拉伸应力层和蚀刻停止层的部分从PMOS器件上除去，留下第二拉伸在NMOS器件上的应力层。

47. 发明授权

US07022561B2 CMOS device 有权
标题翻译： CMOS器件
公开(公告)号：US07022561B2
公开(公告)日：2006-04-04
申请号：US10307619
申请日：2002-12-02
申请人： Chien-Chao Huang , Chao-Hsing Wang , Chung-Hu Ge , Chenming Hu
发明人： Chien-Chao Huang , Chao-Hsing Wang , Chung-Hu Ge , Chenming Hu
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823828
摘要： A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.
摘要翻译：一种方法，包括提供具有邻近PMOS器件的NMOS器件的衬底，并在所述NMOS和PMOS器件上形成第一应力层，其中所述第一应力层包括第一拉伸应力层或压缩应力层。在第一应力层上形成蚀刻停止层，并且从NMOS器件上去除第一应力层和蚀刻停止层的部分，留下PMOS器件上的第一应力层和蚀刻停止层。第二拉伸应力层形成在NMOS器件上并且在第一应力层和蚀刻停止层上方，并且第二拉伸应力层和蚀刻停止层的部分从PMOS器件上除去，留下第二拉伸在NMOS器件上的应力层。

48. 发明申请

US20050133817A1 Improved Cobalt Silicidation Process for Substrates with a Silicon Germanium Layer 有权
标题翻译：具有硅锗层的衬底的改进的钴硅化工艺
公开(公告)号：US20050133817A1
公开(公告)日：2005-06-23
申请号：US10710012
申请日：2004-06-11
申请人： Chien-Chao Huang , Yee-Chia Yeo , Chao-Hsiung Wang , Chun-Chieh Lin , Chenming Hu
发明人： Chien-Chao Huang , Yee-Chia Yeo , Chao-Hsiung Wang , Chun-Chieh Lin , Chenming Hu
IPC分类号： H01L21/285 , H01L21/336 , H01L21/8238 , H01L29/10 , H01L29/76
CPC分类号： H01L29/66636 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L29/1054 , H01L29/665 , H01L29/66545 , Y10S438/933
摘要： A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.
摘要翻译：一种方法包括在半导体衬底上提供半导体合金层，在半导体合金层上形成栅极结构，在半导体衬底的栅极结构的两侧形成源区和漏极区，去除半导体合金层的至少一部分覆盖源极和漏极区域，并且在源极和漏极区域上形成金属硅化物区域。

49. 发明授权

US06900502B2 Strained channel on insulator device 有权
标题翻译：应变绝缘体上的通道
公开(公告)号：US06900502B2
公开(公告)日：2005-05-31
申请号：US10407761
申请日：2003-04-03
申请人： Chung-Hu Ge , Chao-Hsuing Wang , Chien-Chao Huang , Wen-Chin Lee , Chenming Hu
发明人： Chung-Hu Ge , Chao-Hsuing Wang , Chien-Chao Huang , Wen-Chin Lee , Chenming Hu
IPC分类号： H01L21/00 , H01L21/30 , H01L21/762 , H01L21/84 , H01L27/01 , H01L27/12 , H01L29/02 , H01L29/72 , H01L29/772
CPC分类号： H01L21/823807 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L29/7848
摘要： A semiconductor device 10 includes a substrate 12 (e.g., a silicon substrate) with an insulating layer 14 (e.g., an oxide such as silicon dioxide) disposed thereon. A first semiconducting material layer 16 (e.g., SiGe) is disposed on the insulating layer 14 and a second semiconducting material layer 18 (e.g., Si) is disposed on the first semiconducting material layer 16. The first and second semiconducting material layers 16 and 18 preferably have different lattice constants such that the first semiconducting material layer 16 is compressive and the second semiconducting material layer is tensile 18.
摘要翻译：半导体器件10包括其上设置有绝缘层14（例如氧化物如二氧化硅）的衬底12（例如，硅衬底）。第一半导体材料层16（例如，SiGe）设置在绝缘层14上，并且第二半导体材料层18（例如，Si）设置在第一半导体材料层16上。第一和第二半导体材料层16和18优选地具有不同的晶格常数，使得第一半导体材料层16是压缩的，并且第二半导体材料层是拉伸18。

50. 发明授权

US06878610B1 Relaxed silicon germanium substrate with low defect density 有权
标题翻译：具有低缺陷密度的松弛硅锗衬底
公开(公告)号：US06878610B1
公开(公告)日：2005-04-12
申请号：US10228545
申请日：2002-08-27
申请人： Chun Chich Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
发明人： Chun Chich Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
IPC分类号： C30B1/00 , H01L21/00 , H01L21/20 , H01L21/205 , H01L21/324 , H01L21/36 , H01L21/84 , H01L29/10
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/324
摘要： A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe, has been developed. In a first embodiment of this invention the relaxed, low density SiGe layer is epitaxially grown on an silicon layer which in turn is located on an underlying SiGe layer. During the epitaxial growth of the overlying SiGe layer defects are formed in the underlying silicon layer resulting in the desired, relaxation, and decreased defect density for the SiGe layer. A second embodiment features an anneal procedure performed during growth of the relaxed SiGe layer, resulting in additional relaxation and decreased defect density, while a third embodiment features an anneal procedure performed to the underlying silicon layer prior to epitaxial growth of the relaxed SiGe layer, again allowing optimized relaxation and defect density to be realized for the SiGe layer. The ability to obtain a strained silicon layer on a relaxed, low defect density SiGe layer, allows devices with enhanced carrier mobility to be formed in the surface of the strained silicon layer, with decreased risk of leakage due the presence of the underlying, relaxed, low defect density SiGe layer.
摘要翻译：已经开发了在松弛的低缺陷密度半导体合金层如SiGe上形成应变硅层的方法。在本发明的第一实施例中，松散的低密度SiGe层在硅层上外延生长，硅层又位于下面的SiGe层上。在覆盖SiGe层的外延生长期间，在下层硅层中形成缺陷，导致SiGe层所需的，松弛的和降低的缺陷密度。第二个实施例的特征在于在松弛的SiGe层的生长期间执行的退火程序，导致附加的松弛和降低的缺陷密度，而第三实施例的特征在于在弛豫的SiGe层的外延生长之前对下面的硅层进行退火处理允许为SiGe层实现优化的弛豫和缺陷密度。在松弛的低缺陷密度SiGe层上获得应变硅层的能力允许在应变硅层的表面形成具有增强的载流子迁移率的器件，由于存在下面的，放松的，低缺陷密度SiGe层。

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