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41. 发明申请

US20110153908A1 ADAPTIVE ADDRESS MAPPING WITH DYNAMIC RUNTIME MEMORY MAPPING SELECTION 有权
标题翻译：具有动态运行记忆映射选择的自适应地址映射
公开(公告)号：US20110153908A1
公开(公告)日：2011-06-23
申请号：US12646248
申请日：2009-12-23
申请人： Andre Schaefer , Matthias Gries
发明人： Andre Schaefer , Matthias Gries
IPC分类号： G06F12/06 , G06F12/10
CPC分类号： G06F12/10 , G06F12/0607 , Y02D10/13
摘要： A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.
摘要翻译：系统监视并动态地改变计算系统运行时的内存映射。计算系统具有各种存储器资源，以及多种可能的映射，其指示如何将数据存储在存储器资源中并随后从存储器资源访问。在计算设备的不同运行时或负载条件下，每个存储器映射的性能可能不同。内存控制器可以监视当前内存映射的运行时性能，并根据内存映射的监视或观察性能在运行时动态更改内存映射。性能监视可以在系统中从字节级别到存储器通道的任意数量的不同粒度进行修改。

42. 发明申请

US20110078368A1 EFFICIENT CLOCKING SCHEME FOR A BIDIRECTIONAL DATA LINK 有权
标题翻译：双向数据链接的有效时钟方案
公开(公告)号：US20110078368A1
公开(公告)日：2011-03-31
申请号：US12567701
申请日：2009-09-25
申请人： Andre Schaefer
发明人： Andre Schaefer
IPC分类号： G06F1/04 , G06F12/02
CPC分类号： G06F13/1689 , G11C7/1066 , G11C7/222
摘要： A method for communication via a bidirectional data link between a processing device and a memory device. The memory device includes a clock source to generate a clock signal for driving a latching at the memory device of data to and/or from the bidirectional data link. The memory device provides the clock signal to the processing device for driving a latching at the processing device of data to and/or from the bidirectional data link.
摘要翻译：一种用于通过处理设备和存储设备之间的双向数据链路进行通信的方法。存储器件包括时钟源，用于产生时钟信号，用于驱动在存储器件处的数据到和/或来自双向数据链路的锁存。存储装置向处理装置提供时钟信号，用于驱动处理装置处的数据到和/或来自双向数据链路的锁存。

43. 发明申请

US20100332921A1 Fast data eye retraining for a memory 有权
标题翻译：快速数据眼睛重新训练记忆
公开(公告)号：US20100332921A1
公开(公告)日：2010-12-30
申请号：US12459420
申请日：2009-06-30
申请人： Andre Schaefer
发明人： Andre Schaefer
IPC分类号： G11C29/04
CPC分类号： G06F13/1689 , G11C5/04 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C29/02 , G11C29/023 , G11C29/50 , G11C29/50012 , G11C2029/0409 , G11C2207/2254 , Y02D10/14
摘要： A method, device, and system are disclosed. In one embodiment method includes determining a left edge and right edge of a valid data eye for a memory. The method continues by periodically checking the left and right edges for movement during operation of the memory. If movement is detected, the method retrains the valid data eye with an updated left edge and right edge.
摘要翻译：公开了一种方法，装置和系统。在一个实施例中，方法包括确定存储器的有效数据眼睛的左边缘和右边缘。该方法通过在存储器的操作期间周期性地检查左右边缘以进行移动来继续。如果检测到移动，则该方法使用更新的左边缘和右边缘重新训练有效的数据眼睛。

44. 发明申请

US20060170456A1 Driver circuit for binary signals 有权
标题翻译：二进制信号驱动电路
公开(公告)号：US20060170456A1
公开(公告)日：2006-08-03
申请号：US11316379
申请日：2005-12-22
申请人： Andre Schaefer
发明人： Andre Schaefer
IPC分类号： H03K19/094
CPC分类号： H03K17/162 , H03K17/08122
摘要： The invention relates to a driver circuit for binary signals, said circuit having two branch circuits which are connected in parallel with one another between an input node and an output node, the first of which branch circuits contains an output stage which, in response to the first binary value of a binary signal that is applied to the input node, connects the output node to a first logic potential via a first nonreactive resistor, and the second of which branch circuits contains an output stage which, in response to the second binary value of the binary signal that is applied to the input node, connects the output node to a second logic potential via a second nonreactive resistor. According to the invention, the driver circuit contains a duty ratio control device for setting the signal propagation time from the input node to the output stage of one branch circuit relative to the signal propagation time from the input node to the output stage of the other branch circuit.
摘要翻译：本发明涉及一种用于二进制信号的驱动电路，所述电路具有两个分支电路，它们在输入节点和输出节点之间彼此并联连接，其中第一支路电路包含输出级，响应于施加到输入节点的二进制信号的第一二进制值经由第一非反应电阻将输出节点连接到第一逻辑电位，其中第二二进制值包括输出级，响应于第二二进制值施加到输入节点的二进制信号通过第二非反应电阻将输出节点连接到第二逻辑电位。根据本发明，驱动电路包含占空比控制装置，用于相对于从另一分支的输入节点到输出级的信号传播时间，设定从一输入节点到一分支电路的输出级的信号传播时间电路。

45. 发明申请

US20060152957A1 Circuit arrangement and method for setting operating parameters in a RAM module 审中-公开
标题翻译：用于在RAM模块中设置操作参数的电路布置和方法
公开(公告)号：US20060152957A1
公开(公告)日：2006-07-13
申请号：US11258838
申请日：2005-10-26
申请人： Andre Schaefer
发明人： Andre Schaefer
IPC分类号： G11C5/00
CPC分类号： G11C11/4072 , G11C7/20 , G11C2207/2254
摘要： An inventive circuit arrangement for setting selected operating parameters in a RAM module contains, for each element in a set of M different operating parameters, a respective value register which is individually assigned, can be set using an individual control signal and is intended to store an item of value information that has been input for the relevant parameter. A first group of external terminals is dedicated to inputting destination information which indicates the respective parameter to be set, and a second group of external terminals is dedicated to inputting value information for the parameters. Provision is also made of a selection device which can be controlled using the destination information which has been input at the first group of terminals in order to transmit the value information which has been input at the second group of terminals only to that value register which is assigned to the indicated parameter. One advantageous use of the inventive circuit arrangement is a method for individually trimming operating parameters of the data transmission drivers of the RAM module.
摘要翻译：用于在RAM模块中设置所选择的操作参数的本发明的电路装置包含对于M组不同操作参数的一组中的每个元件，可以使用单独的控制信号来设置单独分配的相应值寄存器，并且旨在存储已经为相关参数输入的价值信息项目。第一组外部终端专用于输入指示要设置的各个参数的目的地信息，第二组外部终端专用于输入参数的值信息。还可以使用可以使用在第一组终端输入的目的地信息来控制的选择装置，以便将在第二组终端处输入的值信息仅发送到该值寄存器，该值寄存器是分配给指定的参数。本发明的电路装置的一个有利的用途是用于单独修整RAM模块的数据传输驱动器的操作参数的方法。

46. 发明申请

US20060049511A1 Integrated semiconductor circuit and method for producing an integrated semiconductor circuit 审中-公开
标题翻译：集成半导体电路及其制造方法
公开(公告)号：US20060049511A1
公开(公告)日：2006-03-09
申请号：US11214114
申请日：2005-08-29
申请人： Andre Schaefer
发明人： Andre Schaefer
IPC分类号： H01L23/12
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/05599 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01033 , H01L2924/01068 , H01L2924/01078 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011
摘要： An integrated semiconductor circuit comprises a substrate with a circuit, a plurality of wiring planes that are isolated from one another and from the substrate by insulator layers, and a signal path for the circuit in the substrate and/or the wiring planes. A first contact terminal, which is formed from a stack of metal areas in a plurality of the wiring planes, is designed for connecting the signal path to an external signal source or an external signal receiver during a test of the integrated semiconductor circuit. A second contact terminal, which is formed from a metal area or from a stack of metal areas in a plurality of wiring planes, is designed for connecting the signal path to an external signal source or an external signal receiver during normal operation of the integrated semiconductor circuit. The distance between the metal area or the bottommost metal area of the stack of the second contact terminal and the substrate is greater than the distance between the bottommost metal area of the stack of the first contact terminal and the substrate.
摘要翻译：集成半导体电路包括具有电路的基板，通过绝缘体层彼此隔离并且从基板隔离的多个布线平面以及用于基板和/或布线平面中的电路的信号路径。在多个布线平面中由一堆金属区形成的第一接触端子被设计用于在集成半导体电路的测试期间将信号路径连接到外部信号源或外部信号接收器。第二接触端子由金属区域或多个布线平面中的金属区域堆叠形成，被设计用于在集成半导体的正常操作期间将信号路径连接到外部信号源或外部信号接收器电路。金属区域或第二接触端子的堆叠的最底部金属区域与基板之间的距离大于第一接触端子的堆叠的最底部金属区域与基板之间的距离。

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