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41. 发明申请

US20120023300A1 MEMORY PAGE MANAGEMENT IN A TIERED MEMORY SYSTEM 有权
标题翻译：一个层次化的记忆系统中的存储页面管理
公开(公告)号：US20120023300A1
公开(公告)日：2012-01-26
申请号：US12843718
申请日：2010-07-26
申请人： Robert B. Tremaine , Robert W. Wisniewski
发明人： Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/16 , G06F12/14
CPC分类号： G06F12/1009 , G06F11/3471 , G06F12/1475 , G06F2201/88
摘要： Memory page management in a tiered memory system including a system that includes at least one page table for storing a plurality of entries, each entry associated with a page of memory and each entry including an address of the page and a memory tier of the page. The system also includes a control program configured for allocating pages associated with the entries to a software module, the allocated pages from at least two different memory tiers. The system further includes an agent of the control program capable of operating independently of the control program, the agent configured for receiving an authorization key to the allocated pages, and for migrating the allocated pages between the different memory tiers responsive to the authorization key.
摘要翻译：包括包括至少一个用于存储多个条目的页表的系统的系统中的存储器页面管理，每个条目与存储器页面相关联，每个条目包括页面的地址和页面的存储器层。该系统还包括配置用于将与条目相关联的页面分配给软件模块的控制程序，来自至少两个不同存储器层的所分配的页面。该系统还包括能够独立于控制程序操作的控制程序的代理，被配置为接收对所分配的页面的授权密钥的代理，以及响应于授权密钥在不同存储器层之间迁移分配的页面。

42. 发明申请

US20110161597A1 Combined Memory Including a Logical Partition in a Storage Memory Accessed Through an IO Controller 审中-公开
标题翻译：组合内存包括通过IO控制器访问的存储内存中的逻辑分区
公开(公告)号：US20110161597A1
公开(公告)日：2011-06-30
申请号：US12649856
申请日：2009-12-30
申请人： Robert B. Tremaine , Robert W. Wisniewski
发明人： Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0895
摘要： A computer system having a combined memory. A first logical partition of the combined memory is a main memory region in a storage memory. A second logical partition of the combined memory is a direct memory region in a main memory. A memory controller comprising a storage controller is configured to receive a memory access request including a real address from a processor, determine whether the real address is for the first logical partition or for the second logical partition. If the address is for the first logical partition the storage controller communicates with an IO controller in the storage memory to service the memory access request. If the address is for the direct memory region, the memory controller services the memory access request in a conventional manner.
摘要翻译：具有组合存储器的计算机系统。组合存储器的第一逻辑分区是存储存储器中的主存储器区域。组合存储器的第二逻辑分区是主存储器中的直接存储器区域。包括存储控制器的存储器控制器被配置为从处理器接收包括实际地址的存储器访问请求，确定实际地址是为第一逻辑分区还是用于第二逻辑分区。如果地址是用于第一逻辑分区，则存储控制器与存储器中的IO控制器通信以服务存储器访问请求。如果地址用于直接存储区域，则存储器控制器以常规方式服务存储器访问请求。

43. 发明申请

US20110087834A1 Memory Package Utilizing At Least Two Types of Memories 有权
标题翻译：记忆包利用至少两种类型的记忆
公开(公告)号：US20110087834A1
公开(公告)日：2011-04-14
申请号：US12576028
申请日：2009-10-08
申请人： Robert B. Tremaine
发明人： Robert B. Tremaine
IPC分类号： G06F12/16 , G06F12/02
CPC分类号： G06F12/0638 , Y10S707/99931
摘要： A memory system and methods for memory manage are presented. The memory system includes a volatile memory electrically connected to a high-density memory; a memory controller that expects data to be written or read to or from the memory system at a bandwidth and a latency associated with the volatile memory; a directory within the volatile memory that associates a volatile memory address with data stored in the high-density memory; and redundant storage in the high-density memory that stores a copy of the association between the volatile memory address and the data stored in the high-density memory. The methods for memory management allow writing to and reading from the memory system using a first memory read/write interface (e.g. DRAM interface, etc.), though data is stored in a device of a different memory type (e.g. FLASH, etc.).
摘要翻译：介绍了一种存储器系统和存储器管理方法。存储器系统包括电连接到高密度存储器的易失性存储器; 期望以与易失性存储器相关联的带宽和等待时间从存储器系统写入或读取数据的存储器控制器; 易失性存储器内的目录，其将易失性存储器地址与存储在高密度存储器中的数据相关联; 以及高密度存储器中的冗余存储器，其存储易失性存储器地址和存储在高密度存储器中的数据之间的关联的副本。用于存储器管理的方法允许使用第一存储器读/写接口（例如DRAM接口等）从存储器系统进行写入和读取，尽管数据存储在不同存储器类型（例如FLASH等）的器件中，。

44. 发明授权

US07636813B2 Systems and methods for providing remote pre-fetch buffers 有权
标题翻译：用于提供远程预取缓冲区的系统和方法
公开(公告)号：US07636813B2
公开(公告)日：2009-12-22
申请号：US11419586
申请日：2006-05-22
申请人： Robert B. Tremaine
发明人： Robert B. Tremaine
IPC分类号： G06F13/18 , G06F13/374
CPC分类号： G06F13/1673
摘要： Systems and methods for providing remote pre-fetch buffers. The systems include a computer memory system with a memory controller, one or more memory busses connected to the memory controller, and at least one memory subsystem in communication with the memory controller via the memory busses. The memory controller generates, receives and responds to memory access requests including unsolicited data transfers. The memory subsystem includes one or more memory devices and logic to initiate an unsolicited data transfer to the memory controller based on analysis performed at the memory subsystem of prior memory access requests received by the memory subsystem.
摘要翻译：用于提供远程预取缓冲区的系统和方法。这些系统包括具有存储器控制器的计算机存储器系统，连接到存储器控制器的一个或多个存储器总线以及经由存储器总线与存储器控制器通信的至少一个存储器子系统。存储器控制器生成，接收并响应包括主动请求的数据传输的存储器访问请求。存储器子系统包括一个或多个存储器设备和逻辑，用于基于在存储器子系统处对由存储器子系统接收的先前存储器访问请求执行的分析来发起向存储器控制器的非请求数据传输。

45. 发明授权

US09798528B2 Software solution for cooperative memory-side and processor-side data prefetching 有权
公开(公告)号：US09798528B2
公开(公告)日：2017-10-24
申请号：US11531313
申请日：2006-09-13
申请人： Yaoqing Gao , Gheorghe C. Cascaval , Allan H. Kielstra , Robert B. Tremaine , Michael E. Wazlowski , Lixin Zhang
发明人： Yaoqing Gao , Gheorghe C. Cascaval , Allan H. Kielstra , Robert B. Tremaine , Michael E. Wazlowski , Lixin Zhang
IPC分类号： G06F9/45 , G06F12/0811 , G06F12/08 , G06F12/0862
CPC分类号： G06F8/4442 , G06F8/40 , G06F8/41 , G06F8/443 , G06F8/4441 , G06F12/08 , G06F12/0811 , G06F12/0862 , G06F2212/6028
摘要： A solution for cooperative data prefetching that enables software control of a memory-side data prefetch and/or a processor-side data prefetch is provided. In one embodiment, the invention provides a solution for generating an application, in which access to application data for the application is improved (e.g., optimized) in program code for the application. In particular, a push request, for performing a memory-side data prefetch of the application data, and a prefetch request, for performing a processor-side data prefetch, are added to the program code. The memory-side data prefetch results in the application data being copied from a first data store to a second data store that is faster than the first data store while the processor-side data prefetch results in the application data being copied from the second data store to a third data store that is faster than the second data store.

46. 发明授权

US08869153B2 Quality of service scheduling for simultaneous multi-threaded processors 有权
标题翻译：同步多线程处理器的服务质量调度
公开(公告)号：US08869153B2
公开(公告)日：2014-10-21
申请号：US12130612
申请日：2008-05-30
申请人： Orran Y. Krieger , Bryan S. Rosenburg , Robert B. Tremaine , Robert W. Wisniewski
发明人： Orran Y. Krieger , Bryan S. Rosenburg , Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F9/46 , G06F9/38 , G06F9/50
CPC分类号： G06F9/505 , G06F9/3851 , G06F2209/5018 , G06F2209/5019 , G06F2209/508
摘要： A method and system for providing quality of service guarantees for simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system controls scheduling of the threads based at least partly on the information communicated and provides quality of service guarantees.
摘要翻译：公开了一种用于提供同时多线程处理器的服务质量保证的方法和系统。硬件和操作系统彼此通信，提供与处理元件上执行的线程的线程属性相关的信息。操作系统至少部分地基于传达的信息来控制线程的调度，并提供服务质量保证。

47. 发明申请

US20120066473A1 Memory Architecture with Policy Based Data Storage 失效
标题翻译：基于策略的数据存储的内存架构
公开(公告)号：US20120066473A1
公开(公告)日：2012-03-15
申请号：US12882551
申请日：2010-09-15
申请人： Robert B. Tremaine , Robert W. Wisniewski
发明人： Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/06 , G06F12/10 , G06F13/1694 , Y02D10/13 , Y02D10/14
摘要： A computing system and methods for memory management are presented. A memory or an I/O controller receives a write request where the data two be written is associated with an address. Hint information may be associated with the address and may relate to memory characteristics such as an historical, O/S direction, data priority, job priority, job importance, job category, memory type, I/O sender ID, latency, power, write cost, or read cost components. The memory controller may interrogate the hint information to determine where (e.g., what memory type or class) to store the associated data. Data is therefore efficiently stored within the system. The hint information may also be used to track post-write information and may be interrogated to determine if a data migration should occur and to which new memory type or class the data should be moved.
摘要翻译：介绍了一种用于存储器管理的计算系统和方法。存储器或I / O控制器接收写入请求，其中写入的数据2与地址相关联。提示信息可以与地址相关联，并且可以涉及诸如历史，O / S方向，数据优先级，作业优先级，作业重要性，作业类别，存储器类型，I / O发送者ID，延迟，功率，写入成本或读取成本组件。存储器控制器可以询问提示信息以确定存储关联数据的位置（例如，什么存储器类型或类别）。因此，数据被有效地存储在系统内。提示信息还可以用于跟踪写入后信息，并且可以被询问以确定是否应该发生数据迁移，并且应该向哪个新的存储器类型或类别移动数据。

48. 发明授权

US08051276B2 Operating system thread scheduling for optimal heat dissipation 失效
标题翻译：操作系统线程调度，实现最佳散热
公开(公告)号：US08051276B2
公开(公告)日：2011-11-01
申请号：US11482270
申请日：2006-07-07
申请人： Orran Y. Krieger , Bryan S. Rosenburg , Robert B. Tremaine , Robert W. Wisniewski
发明人： Orran Y. Krieger , Bryan S. Rosenburg , Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F7/38
CPC分类号： G06F9/5033 , G06F1/206 , G06F9/5094 , G06F2209/5013 , G06F2209/5018 , G06F2209/508 , Y02D10/22
摘要： A method and system for thread scheduling for optimal heat dissipation are provided. Temperature sensors measure temperature throughout various parts of a processor chip. The temperatures detected are reported to an operating system or the like for scheduling threads. In one aspect, the observed temperature values are recorded on registers. An operating system or the like reads the registers and schedules threads based on the temperature values.
摘要翻译：提供了一种用于最佳散热的线程调度的方法和系统。温度传感器测量处理器芯片各个部分的温度。检测到的温度被报告给操作系统等用于调度线程。在一个方面，观察到的温度值记录在寄存器上。操作系统等读取寄存器并根据温度值调度线程。

49. 发明申请

US20100250853A1 Prefetch engine based translation prefetching 有权
标题翻译：预取引擎基于翻译预取
公开(公告)号：US20100250853A1
公开(公告)日：2010-09-30
申请号：US11482222
申请日：2006-07-07
申请人： Orran Y. Krieger , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
发明人： Orran Y. Krieger , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/10 , G06F12/08 , G06F13/24
CPC分类号： G06F12/1027 , G06F12/0862 , G06F2212/6028 , G06F2212/651 , G06F2212/654
摘要： A method and system for prefetching in computer system are provided. The method in one aspect includes using a prefetch engine to perform prefetch instructions and to translate unmapped data. Misses to address translations during the prefetch are handled and resolved. The method also includes storing the resolved translations in a respective cache translation table. A system for prefetching in one aspect includes a prefetch engine operable to receive instructions to prefetch data from the main memory. The prefetch engine is also operable to search cache address translation for prefetch data and perform address mapping translation, if the prefetch data is unmapped. The prefetch engine is further operable to prefetch the data and store the address mapping in one or more cache memory, if the data is unmapped.
摘要翻译：提供了一种在计算机系统中预取的方法和系统。该方法在一个方面包括使用预取引擎来执行预取指令并转换未映射的数据。在预取期间解决翻译错误的处理和解决。该方法还包括将分辨的翻译存储在相应的缓存转换表中。用于在一个方面预取的系统包括预取引擎，其可操作以接收从主存储器预取数据的指令。如果预取数据未被映射，则预取引擎还可用于搜索缓存地址转换以获取预取数据并执行地址映射转换。如果数据未被映射，则预取引擎还可操作以预取数据并将地址映射存储在一个或多个高速缓冲存储器中。

50. 发明授权

US07523290B2 Very high speed page operations in indirect accessed memory systems 有权
标题翻译：间接访问存储系统中的高速页面操作
公开(公告)号：US07523290B2
公开(公告)日：2009-04-21
申请号：US10672376
申请日：2003-09-26
申请人： Peter A. Franaszek , Charles O. Schulz , T. Basil Smith , Robert B. Tremaine , Michael Wazlowski
发明人： Peter A. Franaszek , Charles O. Schulz , T. Basil Smith , Robert B. Tremaine , Michael Wazlowski
IPC分类号： G06F12/00
CPC分类号： G06F12/1009
摘要： A computing system and method employing a processor device for generating real addresses associated with memory locations of a real memory system for reading and writing of data thereto, the system comprising: a plurality of memory blocks in the real memory system for storing data, a physical memory storage for storing the pages of data comprising one or more real memory blocks, each real memory block partitioned into one or more sectors, each comprising contiguous bytes of physical memory; a translation table structure in the physical memory storage having entries for associating a real address with sectors of the physical memory, each translation table entry including one or more pointers for pointing to a corresponding sector in its associated real memory block, the table accessed for storing data in one or more allocated sectors for memory read and write operations initiated by the processor; and, a control device for directly manipulating entries in the translation table structure for performing page operations without actually accessing physical memory data contents. In this system, the actual data of the pages involved in the operation are never accessed by the processor and therefore is never required in the memory cache hierarchy, thus eliminating the cache damage normally associated with these block operations. Further the manipulation of the translation table will involve reading and writing a few bytes to perform the operation as opposed to reading and writing the hundreds or thousands of bytes in the pages being manipulated.
摘要翻译：一种计算系统和方法，所述计算系统和方法采用处理器设备来生成与实际存储器系统的存储器位置相关联的用于读取和写入数据的实际地址，所述系统包括：所述实际存储器系统中的用于存储数据的多个存储块，用于存储包括一个或多个实际存储器块的数据页面的存储器存储器，每个实际存储器块被划分成一个或多个扇区，每个扇区包括物理存储器的连续字节; 物理存储器存储器中的转换表结构具有用于将实际地址与物理存储器的扇区相关联的条目，每个转换表条目包括用于指向其相关联的实际存储器块中的对应扇区的一个或多个指针，用于由处理器发起的用于存储器读和写操作的一个或多个分配扇区中的数据; 以及用于直接操纵翻译表结构中的条目以执行页面操作而不实际访问物理存储器数据内容的控制装置。在该系统中，操作所涉及的页面的实际数据从不被处理器访问，因此在存储器高速缓存层次结构中从不需要这样的数据，从而消除通常与这些块操作相关联的高速缓存损坏。此外，翻译表的操作将涉及读取和写入几个字节以执行操作，而不是在被操纵的页面中读取和写入数百或数千字节。

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