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41. 发明授权

US08330477B1 Test engine for integrated circuit chip testing 有权
标题翻译：用于集成电路芯片测试的测试引擎
公开(公告)号：US08330477B1
公开(公告)日：2012-12-11
申请号：US12352439
申请日：2009-01-12
申请人： Albert Wu , Chiping Ai , Hungchi Chen , Bruce Wang , Abdul Elaydi
发明人： Albert Wu , Chiping Ai , Hungchi Chen , Bruce Wang , Abdul Elaydi
IPC分类号： G01R31/00 , G01R31/20
CPC分类号： G01R31/2601 , G01R31/318371 , G01R31/31919 , G06F15/00 , H01L23/544 , H01L2924/0002 , H01L2924/00
摘要： Some of the embodiments of the present disclosure provide an integrated circuit (IC) chip comprising a die, a system on chip (SOC) coupled to the die, and an internal test engine included in the SOC and configured to test the die, wherein one or more components within the IC chip may be configured to be tested by an external test engine coupled to the IC chip. Other embodiments are also described and claimed.
摘要翻译：本公开的一些实施例提供了一种集成电路（IC）芯片，其包括芯片，耦合到管芯的芯片上系统（SOC）和包括在SOC中并被配置为测试裸片的内部测试引擎，其中一个 IC芯片内的多个组件可以被配置为通过耦合到IC芯片的外部测试引擎进行测试。还描述和要求保护其他实施例。

42. 发明申请

US20120098127A1 POWER/GROUND LAYOUT FOR CHIPS 有权
标题翻译：电源/接地布局
公开(公告)号：US20120098127A1
公开(公告)日：2012-04-26
申请号：US13277140
申请日：2011-10-19
申请人： Sehat Sutardja , Chung Chyung Han , Weidan Li , Shuhua Yu , Chuan-Cheng Cheng , Albert Wu
发明人： Sehat Sutardja , Chung Chyung Han , Weidan Li , Shuhua Yu , Chuan-Cheng Cheng , Albert Wu
IPC分类号： H01L23/498 , H01L21/50
CPC分类号： H01L21/76885 , H01L23/3107 , H01L23/5226 , H01L23/5286 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/05647 , H01L2224/061 , H01L2224/16145 , H01L2224/16245 , H01L2224/45111 , H01L2224/45116 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48247 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48847 , H01L2224/731 , H01L2224/85 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.
摘要翻译：本公开的实施例提供一种芯片，其包括形成在第一半导体管芯上的基底金属层和形成在基底金属层上的第一金属层。第一金属层包括被配置为路由芯片中的（i）接地信号或（ii）功率信号中的至少一个的多个岛。芯片还包括形成在第一金属层上的第二金属层。第二金属层包括被配置为路由（i）接地信号或（ii）芯片中的功率信号中的至少一个的多个岛。

43. 发明申请

US20110169163A1 ATTACHING PASSIVE COMPONENTS TO A SEMICONDUCTOR PACKAGE 有权
标题翻译：将无源元件连接到半导体封装
公开(公告)号：US20110169163A1
公开(公告)日：2011-07-14
申请号：US12943673
申请日：2010-11-10
申请人： Shiann-Ming Liou , Albert Wu
发明人： Shiann-Ming Liou , Albert Wu
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L21/565 , H01L23/3121 , H01L23/3128 , H01L23/50 , H01L24/11 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L25/16 , H01L2224/11334 , H01L2224/16113 , H01L2224/16145 , H01L2224/16268 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/48235 , H01L2224/73207 , H01L2224/73265 , H01L2224/81801 , H01L2224/85801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01077 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/1205 , H01L2924/14 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H01L2924/19104 , Y10T29/41 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： Embodiments of the present disclosure provide a method comprising forming an electrically conductive structure on a surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound to encapsulate the semiconductor die, forming an opening in the molding compound, the opening to at least partially expose the electrically conductive structure, and electrically coupling a passive component to the electrically conductive structure through the opening in the molding compound. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了一种方法，包括在半导体管芯的表面上形成导电结构，将半导体管芯附接到基板，形成模制化合物以封装半导体管芯，在模制化合物中形成开口，至少部分地暴露导电结构，并且通过模制化合物中的开口将无源部件电耦合到导电结构。可以描述和/或要求保护其他实施例。

44. 发明授权

US07948818B1 Memory repair system and method 有权
标题翻译：内存修复系统和方法
公开(公告)号：US07948818B1
公开(公告)日：2011-05-24
申请号：US12827446
申请日：2010-06-30
申请人： Albert Wu , Sehat Sutardja
发明人： Albert Wu , Sehat Sutardja
IPC分类号： G11C7/00
CPC分类号： G06F11/0793 , G06F11/073 , G11C29/789
摘要： An integrated circuit (IC) comprises a memory module that stores at least one of data and code. A memory repair database stores data relating to defective memory addresses. A memory control module detects defective memory locations in the memory module, locates redundant memory elements in the memory module, and stores information that associates memory addresses of the defective memory locations with the redundant memory elements in the memory repair database. Storing said information includes electrically altering at least one of a plurality of electrical fuses. A redundant memory decoder module receives the information and physically remaps the memory addresses to the redundant memory locations.
摘要翻译：集成电路（IC）包括存储数据和代码中的至少一个的存储器模块。存储器修复数据库存储与缺陷存储器地址有关的数据。存储器控制模块检测存储器模块中的缺陷存储器位置，将冗余存储器元件定位在存储器模块中，并且存储将缺陷存储器位置的存储器地址与冗余存储器元件关联在存储器修复数据库中的信息。存储所述信息包括电改变多个电保险丝中的至少一个。冗余存储器解码器模块接收信息并将存储器地址物理地映射到冗余存储器位置。

45. 发明授权

US07911053B2 Semiconductor packaging with internal wiring bus 有权
标题翻译：半导体封装内部布线总线
公开(公告)号：US07911053B2
公开(公告)日：2011-03-22
申请号：US12105235
申请日：2008-04-17
申请人： Chenglin Liu , Shiann-Ming Liou , Albert Wu
发明人： Chenglin Liu , Shiann-Ming Liou , Albert Wu
IPC分类号： H01L23/34
CPC分类号： H01L23/50 , H01L23/49531 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/32145 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48111 , H01L2224/48137 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2225/06562 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H04N5/4401 , H04N21/426 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A packaged semiconductor includes inner bond fingers, at least first and second semiconductor dies, and an interposer. The packaged semiconductor further includes wiring between the first and second semiconductor dies and the inner bond fingers, wiring between the interposer and the inner bond fingers, and wiring between the interposer and the first and second semiconductor dies. The wiring between the interposer and the first and second semiconductor dies thereby reduces the count of inner bond fingers needed for the wiring between the first and second semiconductor dies and the inner bond fingers. The interposer further provides indirect access to the inner bond fingers when the inner bond fingers are inaccessible by the first and second semiconductor dies.
摘要翻译：封装半导体包括内键指，至少第一和第二半导体管芯，以及插入件。封装半导体还包括第一和第二半导体管芯与内部接合点之间的布线，插入件与内部接合指状物之间的布线以及插入件与第一和第二半导体管芯之间的布线。插入器与第一和第二半导体管芯之间的布线因此减少了第一和第二半导体管芯与内部接合点之间的布线所需的内部接合指的数量。当内键指不能被第一和第二半导体管芯访问时，插入件进一步提供对内部键合指的间接访问。

46. 发明申请

US20100301467A1 WIREBOND STRUCTURES 审中-公开
标题翻译：电线结构
公开(公告)号：US20100301467A1
公开(公告)日：2010-12-02
申请号：US12786260
申请日：2010-05-24
申请人： Albert Wu
发明人： Albert Wu
IPC分类号： H01L23/49 , H01L23/31 , H01L21/60
CPC分类号： H01L24/05 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2224/0401 , H01L2224/04042 , H01L2224/05082 , H01L2224/05124 , H01L2224/05556 , H01L2224/05557 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/2929 , H01L2224/29339 , H01L2224/45147 , H01L2224/4807 , H01L2224/48091 , H01L2224/48227 , H01L2224/4845 , H01L2224/48465 , H01L2224/48499 , H01L2224/48844 , H01L2224/48855 , H01L2224/48864 , H01L2224/85 , H01L2224/85205 , H01L2924/00011 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2224/78 , H01L2924/00 , H01L2224/48824 , H01L2924/00012 , H01L2924/01006 , H01L2924/0665
摘要： Embodiments of the present disclosure provide an apparatus comprising a semiconductor die, a bond pad formed on the semiconductor die, the bond pad comprising aluminum (Al), a bonding material comprising gold (Au) coupled to the bond pad, the bonding material covering at least a portion of the bond pad, and a wire coupled to the bonding material, the wire comprising copper (Cu). Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了一种包括半导体管芯，形成在半导体管芯上的接合焊盘，包括铝（Al）的接合焊盘，包含耦合到接合焊盘的金（Au））的接合材料的装置，所述接合焊盘的至少一部分以及耦合到所述接合材料的导线，所述导线包括铜（Cu）。可以描述和/或要求保护其他实施例。

47. 发明授权

US07825521B2 Stack die packages 有权
标题翻译：堆栈包装
公开(公告)号：US07825521B2
公开(公告)日：2010-11-02
申请号：US12434264
申请日：2009-05-01
申请人： Albert Wu , Huahung Kao
发明人： Albert Wu , Huahung Kao
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/32145 , H01L2224/45144 , H01L2224/48145 , H01L2224/48227 , H01L2224/731 , H01L2224/73207 , H01L2224/73253 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2924/01079 , H01L2924/14 , H01L2924/00 , H01L2924/00012
摘要： An integrated circuit package includes a substrate comprising a first contact. A first integrated circuit mechanically attached to the substrate. The first integrated circuit comprising a second contact. A first redistribution layer arranged on the first integrated circuit. The first redistribution layer includes a trace coupled to the second contact. A first wire connects the first contact to the second contact. A flip-chip integrated circuit comprises a third contact connected to the trace by a conductive bump. A second integrated circuit mechanically coupled to the flip-chip integrated circuit. The second integrated circuit comprises a fourth contact. A second wire connects the fourth contact to at least the second contact or the first contact.
摘要翻译：集成电路封装包括包括第一触点的基板。机械地附接到基板的第一集成电路。第一集成电路包括第二接触。布置在第一集成电路上的第一再分配层。第一再分配层包括耦合到第二接触的迹线。第一线将第一触点连接到第二触点。倒装芯片集成电路包括通过导电凸块连接到迹线的第三触点。机械耦合到倒装芯片集成电路的第二集成电路。第二集成电路包括第四触点。第二线将第四触点连接到至少第二触点或第一触点。

48. 发明授权

US07704805B1 Fuse structures, methods of making and using the same, and integrated circuits including the same 有权
标题翻译：保险丝结构，制造和使用它们的方法以及包括其的集成电路
公开(公告)号：US07704805B1
公开(公告)日：2010-04-27
申请号：US12012723
申请日：2008-02-04
申请人： Chuan-Cheng Cheng , Shuhua Yu , Roawen Chen , Albert Wu
发明人： Chuan-Cheng Cheng , Shuhua Yu , Roawen Chen , Albert Wu
IPC分类号： H01L21/82 , H01L21/8238 , H01L21/336
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).
摘要翻译：保险丝结构，包括该结构的集成电路，以及使用该保险丝的结构和（重新）配置电路的方法。熔丝结构通常包括（a）具有至少两个电耦合到其上的电路元件的导电结构，（b）导电结构上的电介质层，和（c）第一介电层和导电结构上的第一透镜，以至少部分地将光聚焦到导电结构上。制造该结构的方法通常包括以下步骤：（1）形成电耦合到第一和第二电路元件的导电结构，（2）在其上形成介电层，和（3）在电介质层上或之上形成透镜，在导电结构之上，透镜被配置为至少部分地将光聚焦到导电结构上。（重新）配置电路的方法通常包括以下步骤：（i）在电路表面上或附近照射足够的电气断开位于透镜下方的对应的第一保险丝的至少一个透镜，并且禁用电路的第一配置，以及（ii）在该电路表面上或其附近照射至少一个其他透镜，足以使位于该透镜下方的对应的第二保险丝电气断开并使电路能够进行第二配置。该结构和方法有利地提供具有改善的可靠性和更小的芯片面积的熔丝结构，从而提高制造工艺的产量和每个晶片的模具数量（总和良好）。

49. 发明授权

US07535110B2 Stack die packages 有权
标题翻译：堆栈包装
公开(公告)号：US07535110B2
公开(公告)日：2009-05-19
申请号：US11801317
申请日：2007-05-09
申请人： Albert Wu , Huahung Kao
发明人： Albert Wu , Huahung Kao
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/32145 , H01L2224/45144 , H01L2224/48145 , H01L2224/48227 , H01L2224/731 , H01L2224/73207 , H01L2224/73253 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2924/01079 , H01L2924/14 , H01L2924/00 , H01L2924/00012
摘要： Integrated circuit packages having corresponding methods comprise: a substrate comprising first electric contacts; a first wirebond integrated circuit die mechanically coupled to the substrate and comprising second electric contacts electrically coupled to the first electric contacts of the substrate by first electrically conductive wires; a flip-chip integrated circuit die comprising third electric contacts electrically coupled to the second electric contacts of the first wirebond integrated circuit die by electrically conductive bumps; and a second wirebond integrated circuit die mechanically coupled to the flip-chip integrated circuit die and comprising fourth electric contacts electrically coupled to the second electric contacts of the first wirebond integrated circuit die, or the first electric contacts of the substrate, or both, by second electrically conductive wires.
摘要翻译：具有相应方法的集成电路封装包括：基板，包括第一电触头; 机械耦合到所述衬底并且包括通过第一导电线电耦合到所述衬底的所述第一电触点的第二电触点的第一引线键合集成电路模; 一种倒装芯片集成电路芯片，包括通过导电凸块电耦合到第一引线键合集成电路芯片的第二电触头的第三电触头; 以及第二引线键合集成电路芯片，其机械耦合到所述倒装芯片集成电路管芯并且包括电耦合到所述第一引线键合集成电路管芯的所述第二电触头或所述衬底的所述第一电触点或两者的第四电触点，第二导电线。

50. 发明授权

US08748910B2 Systems and methods for integrating LED displays and LED display controllers 失效
标题翻译：集成LED显示屏和LED显示控制器的系统和方法
公开(公告)号：US08748910B2
公开(公告)日：2014-06-10
申请号：US12965001
申请日：2010-12-10
申请人： Wanfeng Zhang , Albert Wu
发明人： Wanfeng Zhang , Albert Wu
IPC分类号： H01L33/00
CPC分类号： H01L27/156 , H01L2224/48091 , H01L2224/48227 , H05B33/0806 , Y02B20/342 , H01L2924/00014
摘要： A system includes a plurality of light emitting diodes (LEDs) and a control module configured to generate pulse width modulated (PWM) pulses to drive the LEDs. The LEDs and the control module are integrated in an integrated circuit (IC) package.
摘要翻译：一种系统包括多个发光二极管（LED）和被配置为产生脉宽调制（PWM）脉冲以驱动LED的控制模块。 LED和控制模块集成在集成电路（IC）封装中。

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