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41. 发明授权

US07343425B1 Multi-speed serial interface for media access control and physical layer devices 有权
标题翻译：用于媒体访问控制和物理层设备的多速串行接口
公开(公告)号：US07343425B1
公开(公告)日：2008-03-11
申请号：US10646601
申请日：2003-08-21
申请人： William Lo , Nafea Bishara
发明人： William Lo , Nafea Bishara
IPC分类号： G06F15/16
CPC分类号： H04L65/60 , H04L49/3054 , H04L49/352
摘要： A network device includes a media access control (MAC) device that transmits a first data stream at a first data rate that includes symbols having M bits. A translator converts the first data stream to a second data stream at a second data rate. The translator includes a data appender that appends N bits to the symbols in the first data stream to generate second symbols having M+N bits. A data duplicator duplicates the second symbols X times to produce the second data stream at the second data rate.
摘要翻译：网络设备包括以包括具有M比特的符号的第一数据速率发送第一数据流的媒体接入控制（MAC）设备。翻译器以第二数据速率将第一数据流转换为第二数据流。翻译器包括数据追加器，其将N位附加到第一数据流中的符号，以生成具有M + N位的第二符号。数据复制器复制第二符号X次以产生第二数据速率的第二数据流。

42. 发明授权

US07231505B1 Aligning IP payloads on memory boundaries for improved performance at a switch 有权
标题翻译：在内存边界上对齐IP有效载荷，以提高交换机的性能
公开(公告)号：US07231505B1
公开(公告)日：2007-06-12
申请号：US10649187
申请日：2003-08-26
申请人： Nafea Bishara
发明人： Nafea Bishara
IPC分类号： G06F12/02 , G06F12/16 , G06F7/00
CPC分类号： H04L49/604 , H04L69/22
摘要： A network device includes an alignment module to align payloads of received frames on memory boundaries in a buffer memory. The frames may be Ethernet frames which encapsulate IP (Inernet Protocol) packets as payloads. The alignment module prefixes dummy bytes to the frame header to shift the IP payload into an aligned position in the memory regions of the memory.
摘要翻译：网络设备包括对准模块，用于将缓冲存储器中的存储器边界上的接收帧的有效载荷对准。这些帧可以是将IP（Inernet Protocol）分组封装成有效载荷的以太网帧。对准模块将伪字节前缀到帧头部，以将IP有效载荷移位到存储器的存储器区域中的对准位置。

43. 发明授权

US07167942B1 Dynamic random access memory controller 有权
标题翻译：动态随机存取控制器
公开(公告)号：US07167942B1
公开(公告)日：2007-01-23
申请号：US10458049
申请日：2003-06-09
申请人： Nafea Bishara
发明人： Nafea Bishara
IPC分类号： G06F12/00
CPC分类号： G06F12/0607 , G06F13/1678
摘要： An apparatus, and method and computer program thereof, comprises a plurality of ports each adapted to receive packets of data; a memory controller core adapted to generate one or more memory transactions for each of the packets of the data, wherein each memory transaction comprises a payload having a size of m bytes, and wherein the payloads contain the data; a memory comprising a plurality of memory banks adapted to store the data, wherein the memory can receive no more than n bytes of data in a single memory transaction; and a memory interface adapted to transmit the memory transactions to the memory; wherein m=kn and k is an integer.
摘要翻译：一种装置及其方法和计算机程序，包括多个端口，每个端口适于接收数据包; 存储器控制器核心，其适于为数据的每个分组生成一个或多个存储器事务，其中每个存储器事务包括具有m字节大小的有效载荷，并且其中所述有效载荷包含所述数据; 存储器，包括适于存储所述数据的多个存储体，其中所述存储器可以在单个存储器事务中接收不超过n个字节的数据; 以及适于将所述存储器事务发送到所述存储器的存储器接口; 其中m = kn和k是整数。

44. 发明授权

US07120834B1 Fast port failover in a network switch 有权
标题翻译：网络交换机中的快速端口故障切换
公开(公告)号：US07120834B1
公开(公告)日：2006-10-10
申请号：US10353451
申请日：2003-01-28
申请人： Nafea Bishara
发明人： Nafea Bishara
IPC分类号： G06F11/00
CPC分类号： H04L41/0672 , H04L45/22 , H04L47/58 , H04L49/253 , H04L49/552 , H04L49/557
摘要： A network switch, method and computer program product. The network switch comprises a plurality of ports each adapted to exchange frames of data with one or more network devices; a transfer circuit adapted to transfer the frames of the data between the ports; and wherein at least one of the ports comprises a loopback circuit adapted to send to the transfer circuit, when the one of the ports is not operational, each frame of the data received by the one of the ports from the transfer circuit, and a redirect circuit adapted to cause the transfer circuit to transfer, to one or more predetermined others of the ports, when the one of the ports is not operational, each frame of the data received by the transfer circuit from the one of the ports.
摘要翻译：网络交换机，方法和计算机程序产品。网络交换机包括多个端口，每个端口适于与一个或多个网络设备交换数据帧; 适于在端口之间传送数据帧的传送电路; 并且其中所述端口中的至少一个包括回送电路，所述回送电路适于发送到所述传输电路，当所述端口中的一个不可操作时，由所述传输电路中的所述一个端口接收到的数据的每一帧以及重定向电路，其适于使所述传送电路在所述端口中的一个不工作时将所述传输电路的一个或多个预定的其他端口传送到所述传输电路从所述端口之一接收的每个数据帧。

45. 发明授权

US09430379B1 Dynamic random access memory controller 有权
标题翻译：动态随机存取控制器
公开(公告)号：US09430379B1
公开(公告)日：2016-08-30
申请号：US11653731
申请日：2007-01-15
申请人： Nafea Bishara
发明人： Nafea Bishara
IPC分类号： G06F12/00 , G06F12/06
CPC分类号： G06F12/0607 , G06F13/1678
摘要： A memory controller comprises a memory controller core that receives packets of data and generates memory transactions for each of the packets of data. A memory interface transmits each of the memory transactions to one of a plurality of memory banks of a memory. The memory controller directs each of the memory transactions to a different memory bank than an immediately preceding memory transaction.
摘要翻译：存储器控制器包括存储器控制器核心，其接收数据分组并为每个数据分组生成存储器事务。存储器接口将每个存储器事务传送到存储器的多个存储器组之一。存储器控制器将每个存储器事务指向与紧接在前的存储器事务相对应的不同存储器组。

46. 发明授权

US08599859B2 Iterative parsing and classification 失效
标题翻译：迭代解析和分类
公开(公告)号：US08599859B2
公开(公告)日：2013-12-03
申请号：US12947678
申请日：2010-11-16
申请人： Alon Pais , Nafea Bishara
发明人： Alon Pais , Nafea Bishara
IPC分类号： G06F9/26
CPC分类号： H04L45/00 , H04L45/7453 , H04L49/3009
摘要： Some of the embodiments of the present disclosure provide a method comprising performing, by an iterative parser and classifier engine, a first parsing and classification cycle on a data packet, based at least in part on header information of the data packet; generating a first parsing and classification result based at least in part on performing the first parsing and classification cycle; and performing a second parsing and classification cycle on the data packet, based at least in part on header information of the data packet and the first parsing and classification result. Other embodiments are also described and claimed.
摘要翻译：本公开的一些实施例提供了一种方法，其包括至少部分地基于数据分组的报头信息，由迭代解析器和分类器引擎执行数据分组上的第一解析和分类周期; 至少部分地基于执行第一解析和分类周期来生成第一解析和分类结果; 以及至少部分地基于所述数据分组的报头信息和所述第一解析和分类结果对所述数据分组执行第二分析和分类周期。还描述和要求保护其他实施例。

47. 发明授权

US08117503B1 Fast port failover in a network switch 有权
标题翻译：网络交换机中的快速端口故障切换
公开(公告)号：US08117503B1
公开(公告)日：2012-02-14
申请号：US12906911
申请日：2010-10-18
申请人： Nafea Bishara
发明人： Nafea Bishara
IPC分类号： G06F11/00
CPC分类号： H04L41/0672 , H04L45/22 , H04L47/58 , H04L49/253 , H04L49/552 , H04L49/557
摘要： A network switch including a first port, a transfer circuit, and a redirect circuit. The first port is configured to exchange frames of data with a network, the first port configured to operate in a first mode and a second mode. The transfer circuit is configured to transfer the frames of data from the first port to a second port based on information stored in a forwarding table when the first port is operating in the first mode. The redirect circuit is configured to transfer the frames of data to a predetermined backup port associated with the first port when the first port is operating in the second mode.
摘要翻译：一种网络交换机，包括第一端口，传输电路和重定向电路。第一端口被配置为与网络交换数据帧，第一端口被配置为在第一模式和第二模式下操作。传输电路被配置为当第一端口在第一模式下操作时，基于存储在转发表中的信息，将数据帧从第一端口传送到第二端口。重定向电路被配置为当第一端口在第二模式下操作时，将数据帧传送到与第一端口相关联的预定备份端口。

48. 发明授权

US08094668B1 Physical layer device including a serial media independent interface (SMII) 有权
标题翻译：物理层设备包括串行媒体独立接口（SMII）
公开(公告)号：US08094668B1
公开(公告)日：2012-01-10
申请号：US12714746
申请日：2010-03-01
申请人： William Lo , Nafea Bishara
发明人： William Lo , Nafea Bishara
IPC分类号： H04L12/28
CPC分类号： G06F13/385 , H04J3/0697
摘要： A physical layer device includes a serial media independent interface (SMII). The SMII includes a first terminal configured to receive a first data stream. The first data stream is received at the first terminal in accordance with a first frequency. The SMII further includes a transmit circuit configured to (i) sample, on a rising edge of a clock, the first data stream received at the first terminal to generate a second data stream to be transmitted from the physical layer device, and (ii) sample, on a falling edge of the clock, the first data stream received at the first terminal to generate a third data stream to be transmitted from the physical layer device. Each of the second data stream and the third data stream has a second frequency, and the first frequency is twice the second frequency.
摘要翻译：物理层设备包括与串行媒体无关的接口（SMII）。 SMII包括被配置为接收第一数据流的第一终端。第一数据流根据第一频率在第一终端处被接收。 SMII还包括发射电路，其被配置为（i）在时钟的上升沿采样在第一终端处接收的第一数据流，以产生要从物理层设备传输的第二数据流，以及（ii）在时钟的下降沿采样在第一终端处接收的第一数据流，以产生要从物理层设备发送的第三数据流。第二数据流和第三数据流中的每一个具有第二频率，第一频率是第二频率的两倍。

49. 发明授权

US08085778B1 Voltage regulator 有权
标题翻译：路由端口的链路聚合
公开(公告)号：US08085778B1
公开(公告)日：2011-12-27
申请号：US12581512
申请日：2009-10-19
申请人： Yuval Cohen , Nafea Bishara , Michael Orr
发明人： Yuval Cohen , Nafea Bishara , Michael Orr
IPC分类号： H04L12/28
CPC分类号： H04L45/00 , H04L45/24 , H04L45/245 , H04L45/60 , Y02D50/30
摘要： A network device includes a plurality of ports configured to transmit and receive packets of data. A memory is configured to store a routing table. A forwarding engine is configured to transfer the packets of data between the plurality of ports based on the routing table. A processor is configured to define a routing interface. The routing interface comprises a group of the plurality of ports. The processor is configured to assign a media access control (MAC) address to the routing interface. The processor is configured to modify the routing table to direct each packet of data having the media access control (MAC) address as a destination address to a port in the routing interface.
摘要翻译：网络设备包括被配置为发送和接收数据分组的多个端口。存储器被配置为存储路由表。转发引擎被配置为基于路由表在多个端口之间传送数据包。处理器被配置为定义路由接口。路由接口包括一组多个端口。处理器被配置为向路由接口分配媒体访问控制（MAC）地址。处理器被配置为修改路由表以将具有媒体访问控制（MAC）地址的每个数据包作为目的地地址引导到路由接口中的端口。

50. 发明授权

US07983262B1 Efficient IP multicast bridging in ethernet switches 有权
标题翻译：以太网交换机中高效的IP组播桥接
公开(公告)号：US07983262B1
公开(公告)日：2011-07-19
申请号：US12559969
申请日：2009-09-15
申请人： Nafea Bishara
发明人： Nafea Bishara
IPC分类号： H04L12/28
CPC分类号： H04L12/18 , H04L12/56 , H04L45/02 , H04L49/201 , H04L49/351 , H04L49/354
摘要： A switch includes a plurality of ports. A memory stores a bridge table including an entry that associates an Internet Protocol (IP) multicast destination address and an IP source address with a port indicator, which identifies one or more of the plurality of ports. When the switch receives an Ethernet packet comprising an IP multicast packet, a controller generates a key based on an IP multicast destination address and an IP source address associated with the Ethernet packet and performs a lookup on the bridge table using the key. The controller floods the Ethernet packet to the one or more ports identified by the port indicator in response to confirming that the entry is an IP multicast entry and determining that the IP multicast destination address and the IP source address of the entry matches the IP multicast destination address and the IP source address of the Ethernet packet.
摘要翻译：开关包括多个端口。存储器存储包括将互联网协议（IP）组播目的地地址和IP源地址与端口指示符相关联的条目的桥表，所述端口指示符标识所述多个端口中的一个或多个。当交换机接收到包含IP组播数据包的以太网数据包时，控制器将根据IP组播目标地址和与以太网数据包相关联的IP源地址生成一个密钥，并使用密钥对桥表进行查找。控制器响应于确认该条目是IP组播条目并且确定该条目的IP组播目的地地址和该IP条目的IP源地址与该IP组播目的地的IP地址一致，将该以太网分组泛洪到由该端口指示符标识的一个或多个端口地址和以太网数据包的IP源地址。

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