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41. 发明申请

US20090187703A1 MEMORY CARD AND ITS INITIAL SETTING METHOD 有权
标题翻译：记忆卡及其初始设置方法
公开(公告)号：US20090187703A1
公开(公告)日：2009-07-23
申请号：US12412117
申请日：2009-03-26
申请人： HIDEFUMI OODATE , Atsushi Shiraishi , Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori
发明人： HIDEFUMI OODATE , Atsushi Shiraishi , Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori
IPC分类号： G06F12/02 , G06F12/00 , G11C5/14
CPC分类号： G11C16/20
摘要： In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.
摘要翻译：在存储卡1的初始设置中，读出存储在闪速存储器2中的闪存检查数据FD，将该数据FD与先前存储在ROM中的操作检查数据FD11进行比较，存储在存储卡1中的写入检查数据FD12 如果没有检测到故障，ROM 4a被写入闪速存储器2，并且该数据被再次读取并且与写检查数据进行比较。 ROM 4a的FD12。当比较这些数据时没有检测到任何故障时，CPU确定闪存2正常。此外，如果在比较数据中检测到故障，则CPU将复位处理故障数据设置为寄存器5a，以将控制器3设置为睡眠模式。当在此期间接收到命令CMD时，再次执行数据比较。

42. 发明授权

US07451266B2 Nonvolatile memory wear leveling by data replacement processing 失效
标题翻译：通过数据替换处理非易失性存储器损耗均衡
公开(公告)号：US07451266B2
公开(公告)日：2008-11-11
申请号：US11723334
申请日：2007-03-19
申请人： Chiaki Shinagawa , Atsushi Shiraishi , Motoki Kanamori
发明人： Chiaki Shinagawa , Atsushi Shiraishi , Motoki Kanamori
IPC分类号： G06F12/02
CPC分类号： G11C16/3495 , G06F12/0246 , G06F2212/1036 , G06F2212/7211 , G11C16/349
摘要： A risk of data garbling due to cumulative impact of disturbances occurring in memory areas in which no rewrite occurs is to be prevented. A memory device has an erasable and writable nonvolatile memory and a control circuit, wherein the control circuit is enabled to perform processing at a prescribed timing to replace memory areas. The replacement processing is accomplished by writing stored data in a first memory area in which rewriting is relatively infrequent into an unused second memory area, and making the second memory area into which the writing has been done a used area in place of the first memory area. Since this replacement processing is intended to replace memory areas in which rewriting is infrequent with other memory areas as described above, it is possible to prevent the risk of data garbling due to the cumulative impact of disturbances occurring in memory areas in which no rewrite occurs.
摘要翻译：要防止由于不会发生重写的记忆区域中发生的干扰的累积影响而导致数据乱码的风险。存储器件具有可擦写的非易失性存储器和控制电路，其中控制电路能够在规定的时刻执行处理以替换存储区域。替换处理是通过将存储的数据写入第一存储器区域而实现的，其中重写相对不频繁地进入未使用的第二存储器区域，并且使已经完成写入的第二存储器区域用于替代第一存储区域。由于这种替换处理旨在替代如上所述的与其他存储区域重写不频繁的存储区域，所以可以防止由于在不进行重写的存储区域中发生的干扰的累积影响而导致数据乱码的风险。

43. 发明申请

US20080059852A1 MEMORY CARD AND ITS INITIAL SETTING METHOD 有权
标题翻译：记忆卡及其初始设置方法
公开(公告)号：US20080059852A1
公开(公告)日：2008-03-06
申请号：US11877500
申请日：2007-10-23
申请人： Hidefumi Oodate , Atsushi Shiraishi , Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori
发明人： Hidefumi Oodate , Atsushi Shiraishi , Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori
IPC分类号： G11C29/00
CPC分类号： G11C16/20
摘要： In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.
摘要翻译：在存储卡1的初始设置中，读出存储在闪速存储器2中的闪存检查数据FD，该数据FD与先前存储在ROM中的操作检查数据FD1＆lt; 1＆gt; 存储在ROM4a中的写入检查数据FD1＆lt; 2＆gt;如果没有检测到故障则被写入闪速存储器2，并且再次读取该数据并与写入检查进行比较数据。 ROM1a的FD1＆lt; 2＆gt ;. 当比较这些数据时没有检测到任何故障时，CPU确定闪存2正常。此外，如果在数据比较中检测到故障，则CPU将复位过程故障数据设置为寄存器5a以将控制器3设置为睡眠模式。当在此期间接收到命令CMD时，再次执行数据比较。

44. 发明授权

US07061812B2 Memory card 有权
标题翻译：存储卡
公开(公告)号：US07061812B2
公开(公告)日：2006-06-13
申请号：US10815811
申请日：2004-04-02
申请人： Chiaki Shinagawa , Motoki Kanamori , Atsushi Shiraishi
发明人： Chiaki Shinagawa , Motoki Kanamori , Atsushi Shiraishi
IPC分类号： G11C16/04
CPC分类号： G11C16/107 , G06F12/0246 , G06F2212/7201 , G06F2212/7205 , G11C16/16
摘要： Disclosed is a memory card which ensures high-speed data writing operations. The memory card is formed of an erasable and programmable nonvolatile memory and a control circuit. A memory array of the nonvolatile memory has an erasing table including a first flag designating whether a memory area is a vacant area or not in every erasing unit. The control circuit exercises, when the number of memory areas in which the erasable data is written becomes a constant value, pre-erasing control to previously erase the erasable data over the memory area depending on the first flag indicating a vacant area. Since the erasing process is previously executed to the vacant memory area, necessity for insertion of the erasing process just before the writing process using the vacant memory area can be reduced and thereby writing data to the memory card can be highly speeded.
摘要翻译：公开了一种确保高速数据写入操作的存储卡。存储卡由可擦除和可编程的非易失性存储器和控制电路组成。非易失性存储器的存储器阵列具有包括在每个擦除单元中指定存储区域是否为空区域的第一标志的擦除表。控制电路在写入可擦除数据的存储区域的数量变为常数值时，根据指示空闲区域的第一标志，进行预擦除控制以预先擦除存储区域中的可擦除数据。由于先前对空闲存储区域执行擦除处理，所以可以减少在使用空闲存储区域的写入处理之前插入擦除处理的必要性，从而可以高速地将数据写入存储卡。

45. 发明授权

US08051331B2 Memory card and its initial setting method 有权
标题翻译：存储卡及其初始设定方法
公开(公告)号：US08051331B2
公开(公告)日：2011-11-01
申请号：US12412117
申请日：2009-03-26
申请人： Hidefumi Oodate , Atsushi Shiraishi , Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori
发明人： Hidefumi Oodate , Atsushi Shiraishi , Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori
IPC分类号： G06F11/00
CPC分类号： G11C16/20
摘要： In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.
摘要翻译：在存储卡1的初始设置中，读出存储在闪速存储器2中的闪存检查数据FD，将该数据FD与先前存储在ROM中的操作检查数据FD11进行比较，存储在存储卡1中的写入检查数据FD12 如果没有检测到故障，ROM 4a被写入闪速存储器2，并且该数据被再次读取并且与写检查数据进行比较。 ROM 4a的FD12。当比较这些数据时没有检测到任何故障时，CPU确定闪存2正常。此外，如果在比较数据中检测到故障，则CPU将复位处理故障数据设置为寄存器5a，以将控制器3设置为睡眠模式。当在此期间接收到命令CMD时，再次执行数据比较。

46. 发明申请

US20110258427A1 NAVIGATION DEVICE FOR VEHICLE 有权
标题翻译：车辆导航装置
公开(公告)号：US20110258427A1
公开(公告)日：2011-10-20
申请号：US13085544
申请日：2011-04-13
申请人： Motoki Kanamori
发明人： Motoki Kanamori
IPC分类号： G06F9/24 , G06F1/26
CPC分类号： G01C21/26
摘要： A navigation device for a vehicle includes: a memory device including a NAND type flash memory for storing a predetermined program and a boot program and a controller for searching a failure block in the flash memory and managing a corresponding relation between a logic block and a physical block with eliminating failure blocks; a back-up power source; a power source switch for coupling the memory device with the back-up power source; a power source for generating a predetermined voltage with using the back-up power source; a control device energized from the power source with the predetermined voltage so as to be activated; and a power source control device. The control device determines whether activation is performed for the first time. The control device executes a stand-by process, and then, executes a boot process when the activation is performed for the first time. The control device executes the boot process without executing the stand-by process when the activation is after the first time. The power source control device controls the power source to function when the power source control device receives an activation signal from the power source switch. When the power source switch stops the activation signal, the power source control device stops the operation state of the power source.
摘要翻译：一种用于车辆的导航装置包括：存储装置，其包括用于存储预定程序的NAND型闪速存储器和引导程序，以及用于搜索闪速存储器中的故障块并控制逻辑块和物理的对应关系的控制器消除故障块; 备用电源; 用于将存储器件与备用电源耦合的电源开关; 用于使用备用电源产生预定电压的电源; 控制装置从所述电源以预定电压供电以被激活; 和电源控制装置。控制装置确定是否第一次执行激活。控制装置执行待机处理，然后在第一次执行激活时执行引导处理。当第一次激活时，控制设备执行引导过程而不执行待机过程。当电源控制装置从电源开关接收到激活信号时，电源控制装置控制电源的功能。当电源开关停止启动信号时，电源控制装置停止电源的运行状态。

47. 发明申请

US20070186033A1 Nonvolatile memory wear leveling by data replacement processing 失效
标题翻译：通过数据替换处理非易失性存储器损耗均衡
公开(公告)号：US20070186033A1
公开(公告)日：2007-08-09
申请号：US11723334
申请日：2007-03-19
申请人： Chiaki Shinagawa , Atsushi Shiraishi , Motoki Kanamori
发明人： Chiaki Shinagawa , Atsushi Shiraishi , Motoki Kanamori
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G11C16/3495 , G06F12/0246 , G06F2212/1036 , G06F2212/7211 , G11C16/349
摘要： A risk of data garbling due to cumulative impact of disturbances occurring in memory areas in which no rewrite occurs is to be prevented. A memory device has an erasable and writable nonvolatile memory and a control circuit, wherein the control circuit is enabled to perform processing at a prescribed timing to replace memory areas. The replacement processing is accomplished by writing stored data in a first memory area in which rewriting is relatively infrequent into an unused second memory area, and making the second memory area into which the writing has been done a used area in place of the first memory area. Since this replacement processing is intended to replace memory areas in which rewriting is infrequent with other memory areas as described above, it is possible to prevent the risk of data garbling due to the cumulative impact of disturbances occurring in memory areas in which no rewrite occurs.
摘要翻译：要防止由于不会发生重写的记忆区域中发生的干扰的累积影响而导致数据乱码的风险。存储器件具有可擦写的非易失性存储器和控制电路，其中控制电路能够在规定的时刻执行处理以替换存储区域。替换处理通过将存储的数据写入第一存储器区域来实现，在第一存储器区域中重写相对不频繁地进入未使用的第二存储器区域，并且使已经完成了写入的第二存储器区域被替换为第一存储区域。由于这种替换处理旨在替代如上所述的与其他存储区域重写不频繁的存储区域，所以可以防止由于在不进行重写的存储区域中发生的干扰的累积影响而导致数据乱码的风险。

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