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41. 发明授权

US06716687B2 FET having epitaxial silicon growth 有权
标题翻译：具有外延硅生长的FET
公开(公告)号：US06716687B2
公开(公告)日：2004-04-06
申请号：US10073723
申请日：2002-02-11
申请人： Zhongze Wang , Chih-Chen Cho , Er-Xuan Ping
发明人： Zhongze Wang , Chih-Chen Cho , Er-Xuan Ping
IPC分类号： H01L2184
CPC分类号： H01L29/66651 , H01L21/76264 , H01L29/0653
摘要： Field-effect transistors, and methods of their fabrication, having channel regions formed separately from their source/drain regions and having monocrystalline material interposed between the channel regions and the source/drain regions. The monocrystalline material includes monocrystalline silicon and silicon-germanium alloy.
摘要翻译：场效应晶体管及其制造方法具有与其源/漏区分开形成的沟道区，并且具有介于沟道区和源/漏区之间的单晶材料。单晶材料包括单晶硅和硅 - 锗合金。

42. 发明授权

US06448129B1 Applying epitaxial silicon in disposable spacer flow 有权
公开(公告)号：US06448129B1
公开(公告)日：2002-09-10
申请号：US09490261
申请日：2000-01-24
申请人： Chih-Chen Cho , Er-Xuan Ping
发明人： Chih-Chen Cho , Er-Xuan Ping
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/28525 , H01L21/823418 , H01L21/823468 , H01L21/823481 , H01L27/105 , H01L27/10873 , H01L27/11526 , H01L27/11546 , H01L29/66636
摘要： A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of the transistor gates; forming temporary oxide spacers on the generally vertical sidewalls of the transistor gates; after the step of forming temporary spacers, implanting a second type of conductive dopants into the exposed silicon regions to form source/drain regions of the active transistors; after the step of implanting a second type of conductive dopants, growing an epitaxial silicon over exposed silicon regions; removing the temporary oxide spacers; and forming permanent nitride spacers on the generally vertical sidewalls of the transistor gates.

43. 发明授权

US06218311B1 Post-etch treatment of a semiconductor device 有权
标题翻译：半导体器件的蚀刻后处理
公开(公告)号：US06218311B1
公开(公告)日：2001-04-17
申请号：US09334992
申请日：1999-06-17
申请人： Jeffrey A. McKee , Ming J. Hwang , Chih-Chen Cho , William R. McKee
发明人： Jeffrey A. McKee , Ming J. Hwang , Chih-Chen Cho , William R. McKee
IPC分类号： H01L21302
CPC分类号： H01L29/4941 , H01L21/28123 , H01L21/28176
摘要： Post-etch treatment of an etch-damaged semiconductor device includes forming a protective cover (48, 148) over an oxidizable section (18, 118) of the semiconductor device. The protective cover (48, 148) is operable to at least inhibit oxidation of the oxidizable section (18, 118). While the oxidizable section (18, 118) is covered, an oxide structure (52, 152) is formed. The oxide structure (52, 152) is operable to at least ameliorate etch damage to the semiconductor device.
摘要翻译：蚀刻损坏的半导体器件的蚀刻后处理包括在半导体器件的可氧化部分（18,118）上形成保护盖（48,148）。保护罩（48,148）可操作以至少抑制可氧化部分（18,118）的氧化。当可氧化部分（18,118）被覆盖时，形成氧化物结构（52,152）。氧化物结构（52,152）可操作以至少改善对半导体器件的蚀刻损伤。

44. 发明授权

US5824603A Method of forming a low-K layer in an integrated circuit 失效
标题翻译：在集成电路中形成低K层的方法
公开(公告)号：US5824603A
公开(公告)日：1998-10-20
申请号：US483422
申请日：1995-06-07
申请人： Chih-Chen Cho
发明人： Chih-Chen Cho
IPC分类号： H01L21/02 , H01L21/311 , H01L21/312 , H01L21/302
CPC分类号： H01L28/40 , H01L21/31138 , H01L21/312 , Y10S428/901 , Y10T428/24917 , Y10T428/3154 , Y10T428/31544
摘要： This is a device and method of forming such, wherein the device has an amorphous "TEFLON" (TFE AF) layer. The device comprising: a substrate; a TFE AF 44 layer on top of the substrate; and a semiconductor layer 42 on top of the TFE AF 44 layer. The device may be an electronic or optoelectronic device. The semiconductor layer may be a metal or other substance.
摘要翻译：这是一种形成这种装置和方法，其中该装置具有非晶“TEFLON”（TFE AF）层。该装置包括：基板; TFE AF 44层; 以及在TFE AF 44层的顶部上的半导体层42。该装置可以是电子或光电子装置。半导体层可以是金属或其它物质。

45. 发明授权

US5753040A Method for the growth of epitaxial metal-insulator-metal-semiconductor structures 失效
标题翻译：外延金属 - 绝缘体 - 金属 - 半导体结构的生长方法
公开(公告)号：US5753040A
公开(公告)日：1998-05-19
申请号：US474618
申请日：1995-06-07
申请人： Chih-Chen Cho
发明人： Chih-Chen Cho
IPC分类号： H01L21/28 , H01L21/285 , H01L21/314 , H01L21/3205 , H01L29/51 , C30B23/08
CPC分类号： H01L21/28194 , H01L21/28512 , H01L21/314 , H01L21/32051 , H01L29/51
摘要： In one form of the invention, a method for the growth of an epitaxial insulator-metal structure on a semiconductor surface comprising the steps of maintaining the semiconductor surface at a pressure below approximately 1.times.10.sup.-7 mbar, maintaining the semiconductor surface at a substantially fixed first temperature between approximately 25.degree. C. and 400.degree. C., depositing an epitaxial metal layer on the semiconductor surface, adjusting the semiconductor surface to a substantially fixed second temperature between approximately 25.degree. C. and 200.degree. C., starting a deposition of epitaxial CaF.sub.2 on the first metal layer, ramping the second temperature to a third substantially fixed temperature between 200.degree. C. and 500.degree. C. over a time period, maintaining the third temperature until the epitaxial CaF.sub.2 has deposited to a desired thickness, and stopping the deposition of epitaxial CaF.sub.2 on the first metal layer. Other devices, systems and methods are also disclosed.
摘要翻译：在本发明的一种形式中，一种用于在半导体表面上生长外延绝缘体 - 金属结构的方法包括以下步骤：将半导体表面保持在低于约1×10-7毫巴的压力，将半导体表面保持在基本固定的第一在约25℃至400℃之间的温度下，在半导体表面上沉积外延金属层，将半导体表面调节至约25℃至200℃之间的基本固定的第二温度，开始沉积外延 CaF2在第一金属层上，在一段时间内将第二温度升至第二温度至200℃至500℃之间的第三基本上固定的温度，保持第三温度，直到外延CaF 2沉积到期望的厚度，并停止在第一金属层上沉积外延CaF 2。还披露了其他设备，系统和方法。

46. 发明授权

US5723872A Mixed barrier resonant tunneling 失效
标题翻译：混合屏障共振隧穿
公开(公告)号：US5723872A
公开(公告)日：1998-03-03
申请号：US290269
申请日：1994-08-15
申请人： Alan C. Seabaugh , Chih-Chen Cho
发明人： Alan C. Seabaugh , Chih-Chen Cho
IPC分类号： H01L29/88 , H01L29/06 , H01L29/24
CPC分类号： B82Y10/00 , H01L29/882
摘要： A resonant tunneling diode (400) made of a quantum well (406) with tunneling barriers (404, 408) made of two different materials such as calcium fluoride (408) and silicon dioxide (404). The calcium fluoride provides lattice match between the emitter (410) and the quantum well (406). Further resonant tunneling diodes with silicon lattice match barriers may be made of III-V compounds containing nitrogen.
摘要翻译：由量子阱（406）制成的谐振隧道二极管（400），其具有由诸如氟化钙（408）和二氧化硅（404）的两种不同材料制成的隧道势垒（404,408）。氟化钙在发射极（410）和量子阱（406）之间提供晶格匹配。具有硅晶格匹配屏障的其它谐振隧穿二极管可以由含有氮的III-V化合物制成。

47. 发明授权

US5661344A Porous dielectric material with a passivation layer for electronics applications 失效
标题翻译：多孔电介质材料，具有电子应用的钝化层
公开(公告)号：US5661344A
公开(公告)日：1997-08-26
申请号：US476164
申请日：1995-06-07
申请人： Robert H. Havemann , Bruce E. Gnade , Chih-Chen Cho
发明人： Robert H. Havemann , Bruce E. Gnade , Chih-Chen Cho
IPC分类号： H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L51/00
CPC分类号： H01L21/02216 , H01L21/02126 , H01L21/02203 , H01L21/02282 , H01L21/02304 , H01L21/02337 , H01L21/02343 , H01L21/02359 , H01L21/02362 , H01L21/31695 , H01L21/76802 , H01L21/7682 , H01L21/76829 , H01L21/76831 , H01L23/5222 , H01L23/53223 , H01L2221/1047 , H01L2924/0002
摘要： A semiconductor device and process for making the same are disclosed which use porous dielectric materials to reduce capacitance between conductors, while allowing conventional photolithography and metal techniques and materials to be used in fabrication. In one structure, patterned conductors 18 are provided on an interlayer dielectric 10, with a substrate encapsulation layer 31 deposited conformally over this structure. A layer of porous dielectric material 22 (e.g. dried SiO.sub.2 gel) is then deposited to substantially fill the gaps between and also cover the conductors. A substantially solid cap layer 14 of a material such as SiO.sub.2 is then deposited, followed by a photolithography step to define via locations. Vias are etched through the cap layer, and then through the porous dielectric. A via passivating layer 30 is conformally deposited and then anisotropically etched to clear the bottom of the vias while leaving a passivating liner in the via, preventing the via metal from directly contacting the porous material. A second application of these steps may be used to form a second, overlying structure of patterned conductors 38, encapsulating layer 36, porous dielectric layer 40, and cap layer 42.
摘要翻译：公开了一种半导体器件及其制造方法，其使用多孔介电材料来减小导体之间的电容，同时允许常规光刻和金属技术和材料用于制造。在一种结构中，图案化导体18设置在层间电介质10上，基底封装层31保形地沉积在该结构上。然后沉积一层多孔电介质材料22（例如干燥的SiO 2凝胶）以基本上填充导体之间的间隙并且还覆盖导体。然后沉积诸如SiO 2的材料的基本上固体的盖层14，然后沉积光刻步骤以限定通孔位置。通孔通过盖层蚀刻，然后通过多孔电介质。通孔钝化层30被共形沉积，然后各向异性蚀刻以清除通孔的底部，同时在通孔中留下钝化衬垫，防止通孔金属直接接触多孔材料。可以使用这些步骤的第二应用来形成图案化导体38，封装层36，多孔介电层40和盖层42的第二覆盖结构。

48. 发明授权

US5656848A High thermal resistance backfill material for hybrid UFPA's 失效
标题翻译：用于混合UFPA的高耐热回填材料
公开(公告)号：US5656848A
公开(公告)日：1997-08-12
申请号：US477004
申请日：1995-06-07
申请人： Howard R. Beratan , Chih-Chen Cho
发明人： Howard R. Beratan , Chih-Chen Cho
IPC分类号： G01J5/20 , G01J5/34 , H01L23/532 , H01L27/146 , H01L31/058 , H01L31/09 , H01L31/101
CPC分类号： G01J5/20 , G01J5/34 , H01L23/5329 , H01L27/14609 , H01L27/14623 , H01L27/1465 , H01L27/1469 , H01L2924/0002
摘要： A porous film 64 is used to thermally insulate sensing integrated circuitry 44 from pixels 34 of an uncooled IR detector hybrid system 30. The porous film 64 is preferably a silicon-dioxide xerogel. A protective film 65 may be deposited on the porous film 64.
摘要翻译：多孔膜64用于将感测集成电路44与未经IR的IR检测器混合系统30的像素34热绝缘。多孔膜64优选为二氧化硅干凝胶。保护膜65可以沉积在多孔膜64上。

49. 发明授权

US5656555A Modified hydrogen silsesquioxane spin-on glass 失效
标题翻译：改性氢倍半硅氧烷旋涂玻璃
公开(公告)号：US5656555A
公开(公告)日：1997-08-12
申请号：US390181
申请日：1995-02-17
申请人： Chih-Chen Cho
发明人： Chih-Chen Cho
IPC分类号： C09D183/05 , C09D183/04 , H01L21/312 , H01L21/316
CPC分类号： H01L21/02134 , H01L21/02282 , H01L21/02337 , H01L21/3124
摘要： A modified hydrogen silsesquioxane (HSQ) precursor is disclosed, along with methods for depositing such a precursor on a semiconductor substrate and a semiconductor device having a dielectric thin film deposited from such a precursor. The method comprises coating a semiconductor substrate 10, which typically comprises conductors 12, with a film of a modified HSQ film precursor. The HSQ film precursor comprises a hydrogen silsesquioxane resin and a modifying agent, preferably selected from the group consisting of alkyl alkoxysilanes, fluorinated alkyl alkoxysilanes, and combinations thereof. The method further comprises curing film 14, wherein the inclusion of the modifying agent inhibits oxidation and/or water absorption by the film during and/or after curing. It is believed that the modifying agent modifies film surface 16 to produce this effect. Films produced according to the present invention apparently have repeatable dielectric properties for drying and curing conditions which produced widely varying properties for unmodified films.
摘要翻译：公开了改进的氢倍半硅氧烷（HSQ）前体，以及在半导体衬底上沉积这种前体的方法以及具有由这种前体沉积的电介质薄膜的半导体器件。该方法包括将通常包含导体12的半导体衬底10与改性的HSQ膜前体的膜一起涂覆。 HSQ膜前体包含氢倍半硅氧烷树脂和改性剂，优选选自烷基烷氧基硅烷，氟化烷基烷氧基硅烷及其组合。该方法还包括固化膜14，其中包含改性剂在固化期间和/或固化后抑制膜的氧化和/或吸水。据信，改性剂改变膜表面16以产生这种效果。根据本发明生产的膜显然具有可重复的介电性能，用于干燥和固化条件，其产生对未改性膜的广泛变化的性质。

50. 发明授权

US5627082A High thermal resistance backfill material for hybrid UFPA's 失效
公开(公告)号：US5627082A
公开(公告)日：1997-05-06
申请号：US412817
申请日：1995-03-29
申请人： Howard R. Beratan , Chih-Chen Cho
发明人： Howard R. Beratan , Chih-Chen Cho
IPC分类号： G01J5/20 , G01J5/34 , H01L23/532 , H01L27/146 , H01L31/00 , H01L31/15
CPC分类号： G01J5/20 , G01J5/34 , H01L23/5329 , H01L27/14609 , H01L27/14623 , H01L27/1465 , H01L27/1469 , H01L2924/0002
摘要： A porous film 64 is used to thermally insulate sensing integrated circuitry 44 from pixels 34 of an uncooled IR detector hybrid system 30. The porous film 64 is preferably a silicon-dioxide xerogel. A protective film 65 may be deposited on the porous film 64.

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