专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US5793058A Multi-gate offset source and drain field effect transistors and methods of operating same 失效
标题翻译：多栅极偏移源极和漏极场效应晶体管及其工作方式相同
公开(公告)号：US5793058A
公开(公告)日：1998-08-11
申请号：US692924
申请日：1996-07-31
申请人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park , Keun-Ho Jang , Jae-Hong Jun
发明人： Min-Koo Han , Byung-Hyuk Min , Cheol-Min Park , Keun-Ho Jang , Jae-Hong Jun
IPC分类号： H01L29/70 , H01L21/336 , H01L29/08 , H01L29/78 , H01L29/786 , H01L29/788
CPC分类号： H01L29/6675 , H01L29/0847 , H01L29/7831 , H01L29/7833 , H01L29/78621 , H01L29/78645 , H01L29/788
摘要： A field effect transistor includes laterally spaced apart source and drain regions in a substrate, laterally spaced apart undoped regions in the substrate between the laterally spaced apart source and drain regions, a doped channel region in the substrate between the laterally spaced apart undoped regions, and a gate insulating layer on the substrate. A main gate is on the gate insulating layer opposite the channel, and first and second sub gates are on the gate insulating layer, a respective one of which is opposite a respective one of the spaced apart undoped regions. The first and second sub gates are laterally spaced apart from and electrically insulated from the main gate. The transistor may be formed by patterning a photoresist layer and a gate layer to form a main gate and first and second sub gates, reflowing the photoresist into the lateral space between the main gate and the first and second sub gates, etching the gate insulating layer using the reflowed photoresist as a mask, and implanting ions into the substrate to form source and drain regions using the etched gate insulating layer as a mask.
摘要翻译：场效应晶体管包括在衬底中的横向间隔开的源极和漏极区域，在横向间隔开的源极和漏极区域之间的衬底中横向间隔开的未掺杂区域，在横向间隔开的未掺杂区域之间的衬底中的掺杂沟道区域，以及基板上的栅极绝缘层。主栅极在与沟道相对的栅极绝缘层上，第一和第二子栅极位于栅极绝缘层上，其相应的一个与相应的一个间隔开的未掺杂区域相对。第一和第二子门与主门横向间隔开并与之绝缘。可以通过图案化光致抗蚀剂层和栅极层来形成晶体管，以形成主栅极和第一和第二子栅极，将光致抗蚀剂回流到主栅极和第一和第二子栅极之间的横向空间中，蚀刻栅极绝缘层使用回流光致抗蚀剂作为掩模，并且使用蚀刻的栅绝缘层作为掩模将离子注入到衬底中以形成源区和漏区。

42. 发明授权

US5728593A Power insulated-gate transistor having three terminals and a manufacturing method thereof 失效
标题翻译：具有三个端子的功率绝缘栅晶体管及其制造方法
公开(公告)号：US5728593A
公开(公告)日：1998-03-17
申请号：US496696
申请日：1995-06-29
申请人： Chong-Man Yun , Min-Koo Han , Kwang-Hoon Oh , Deok-Joong Kim
发明人： Chong-Man Yun , Min-Koo Han , Kwang-Hoon Oh , Deok-Joong Kim
IPC分类号： H01L21/76 , H01L21/331 , H01L29/739 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66333 , H01L29/7395 , H01L29/7396
摘要： The present invention relates to a method of manufacturing an insulated-gate transistor including a very thin P.sup.- layer as a channel under a gate terminal. The device and method differs from conventional devices and techniques in that the P.sup.- regions are formed by double diffusion. Secondly, the present invention includes channel regions by forming the N.sup.+ regions in the middle of the shallow P.sup.- layer causing the resistance of the JFET regions to be reduced. High-speed operation of the device can be obtained by reducing the input and reverse capacitances which thereby reduces the time delay when power is supplied. The forward voltage drop is reduced by reducing the resistance of the first conductive semiconductor region which is determined by the distance between the second conductive type semiconductor region in its forward turn-on state.
摘要翻译：本发明涉及一种制造绝缘栅晶体管的方法，该绝缘栅晶体管包括非常薄的P层作为栅极端子下的沟道。该装置和方法与传统的装置和技术不同之处在于P-区通过双重扩散形成。其次，本发明通过在浅P层的中间形成N +区域来包括沟道区域，从而减小JFET区域的电阻。通过减少输入和反向电容可以获得器件的高速操作，从而减少了供电时的延时。通过降低第一导电半导体区域的电阻来减小正向压降，该电阻由第二导电类型半导体区域在其正向导通状态中的距离确定。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式