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41. 发明授权

US4412142A Integrated circuit incorporating low voltage and high voltage semiconductor devices 失效
标题翻译：具有低电压和高压半导体器件的集成电路
公开(公告)号：US4412142A
公开(公告)日：1983-10-25
申请号：US219824
申请日：1980-12-24
申请人： Louis J. Ragonese , Nicholas A. Schmitz , Saverio F. Bevacqua , King Owyang
发明人： Louis J. Ragonese , Nicholas A. Schmitz , Saverio F. Bevacqua , King Owyang
IPC分类号： H01L27/02 , H01L27/082 , H03K17/28 , H03K17/615 , H03K17/795 , H01L27/04 , H03K19/091
CPC分类号： H03K17/795 , H01L27/0244 , H01L27/0821 , H01L27/0825 , H03K17/28 , H03K17/615
摘要： An integrated circuit incorporating high voltage semiconductor devices which are controlled by low voltage semiconductor devices is disclosed, including a method for making the same. The low voltage devices which are capable of realizing complex logic functions on the same chip are realized with only one simple extra step in the fabrication process as compared with the process used to fabricate discrete high voltage power transistors. The process addition to implant the low voltage device does not significantly degrade the original capability associated with discrete power transistors. Both laterally developed and vertically developed devices are described. The integrated circuit combines I.sup.2 L logic with power Darlington transistors. A large area ion implantation permits one to fabricate both low and high voltage devices on one substrate. The resulting integrated circuit permits a plurality of loads to be controlled by a simple or complex control function.
摘要翻译：公开了一种包含由低电压半导体器件控制的高电压半导体器件的集成电路，包括其制造方法。与用于制造离散高压功率晶体管的工艺相比，能够在同一芯片上实现复杂逻辑功能的低电压器件在制造过程中只需一个简单的额外步骤。植入低电压器件的加工过程不会显着降低与分立功率晶体管相关的原始能力。描述了侧向显影和垂直显影的装置。集成电路将I2L逻辑与功率达林顿晶体管相结合。大面积离子注入允许在一个衬底上制造低压和高压器件。所得到的集成电路允许通过简单或复杂的控制功能来控制多个负载。

42. 发明申请

US20090278176A1 HIGH CURRENT DENSITY POWER FIELD EFFECT TRANSISTOR 有权
标题翻译：高电流密度功率场效应晶体管
公开(公告)号：US20090278176A1
公开(公告)日：2009-11-12
申请号：US12119367
申请日：2008-05-12
申请人： Jian Li , King Owyang
发明人： Jian Li , King Owyang
IPC分类号： H01L27/06
CPC分类号： H01L27/085 , H01L29/0623 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/47 , H01L29/7828 , H01L29/8083
摘要： An ultra-short channel hybrid power field effect transistor (FET) device lets current flow from bulk silicon without npn parasitic. This device does not have body but still have body diode with low forward voltage at high current rating. The device includes a JFET component, a first accumulation MOSFET disposed adjacent to the JFET component, and a second accumulation MOSFET disposed adjacent to the JFET component at the bottom of the trench end, or a MOSFET with an isolated gate connecting the source.
摘要翻译：超短通道混合功率场效应晶体管（FET）器件允许电流从体硅流入，而无npn寄生。该器件没有机身，但仍具有在高额定电流下具有低正向电压的体二极管。该器件包括JFET部件，与JFET部件相邻设置的第一累积MOSFET，以及在沟槽端的底部邻近JFET部件设置的第二累积MOSFET，或具有连接源极的隔离栅极的MOSFET。

43. 发明授权

US4794432A Mosfet structure with substrate coupled source 失效
标题翻译： Mosfet结构与衬底耦合源
公开(公告)号：US4794432A
公开(公告)日：1988-12-27
申请号：US7034
申请日：1987-01-27
申请人： Hamza Yilmaz , King Owyang , Robert G. Hodgins
发明人： Hamza Yilmaz , King Owyang , Robert G. Hodgins
IPC分类号： H01L29/10 , H01L29/417 , H01L29/78 , H01L27/02
CPC分类号： H01L29/7816 , H01L29/1087 , H01L29/1095 , H01L29/4175 , H01L29/7802 , H01L29/42368
摘要： A disclosed MOSFET cell has a source region formed at the top surface of a semiconductor substrate. The top surface source region is electrically coupled to a conductive region at a bottom portion of the substrate by means of a vertical conduit which projects through the substrate from the top surface to the conductive region. A current exchanger is provided extending over the top surface of the substrate and coupling a top surface portion of the vertical conduit to the source region. The current exchanger makes ohmic contact with the source region and with the conduit region and shorts the two regions together such that majority carrier current of the conduit region will be "converted" into majority carrier current of the source region and electrical continuity between the source region and the conductive region of the substrate is established. Respective source regions of multiple MOSFET cells may be interconnected in accordance with this method through a longitudinally extending conductive layer which is typically formed near the bottom surface of semiconductor substrates.
摘要翻译：所公开的MOSFET单元具有形成在半导体衬底的顶表面处的源极区域。顶表面源区域通过垂直导管电耦合到衬底的底部的导电区域，该垂直导管从衬底从顶表面突出到导电区域。提供了一种电流交换器，其在衬底的顶表面上延伸并将垂直导管的顶表面部分耦合到源区。电流交换器与源极区域和导管区域形成欧姆接触并且将两个区域一起短路，使得导管区域的多数载流子电流将被“转换”为源极区域的多数载流子电流，并且源极区域之间的电连续性并且建立基板的导电区域。根据该方法，多个MOSFET单元的各个源极区域可以通过纵向延伸的导电层互连，该导电层通常形成在半导体衬底的底表面附近。

44. 发明授权

US4475280A Method of making an integrated circuit incorporating low voltage and high voltage semiconductor devices 失效
标题翻译：制造集成了低压和高压半导体器件的集成电路的方法
公开(公告)号：US4475280A
公开(公告)日：1984-10-09
申请号：US450687
申请日：1982-12-17
申请人： Louis J. Ragonese , Nicholas A. Schmitz , Saverio F. Bevacqua , King Owyang
发明人： Louis J. Ragonese , Nicholas A. Schmitz , Saverio F. Bevacqua , King Owyang
IPC分类号： H01L27/02 , H01L27/082 , H03K17/28 , H03K17/60 , H03K17/795 , H01L21/80
CPC分类号： H01L27/0244 , H01L27/0821 , H01L27/0825 , H03K17/28 , H03K17/60 , H03K17/795
摘要： An integrated circuit incorporating high voltage semiconductor devices which are controlled by low voltage semiconductor devices is disclosed, including a method for making the same. The low voltage devices which are capable of realizing complex logic functions on the same chip are realized with only one simple extra step in the fabrication process as compared with the process used to fabricate discrete high voltage power transistors. The process addition to implant the low voltage device does not significantly degrade the original capability associated with discrete power transistors. Both laterally developed and vertically developed devices are described. The integrated circuit combines I.sup.2 L logic with power Darlington transistors. A large area ion implantation permits one to fabricate both low and high voltage devices on one substrate. The resulting integrated circuit permits a plurality of loads to be controlled by a simple or complex control function.
摘要翻译：公开了一种包含由低电压半导体器件控制的高电压半导体器件的集成电路，包括其制造方法。与用于制造离散高压功率晶体管的工艺相比，能够在同一芯片上实现复杂逻辑功能的低电压器件在制造过程中只需一个简单的额外步骤。植入低电压器件的加工过程不会显着降低与分立功率晶体管相关的原始能力。描述了侧向显影和垂直显影的装置。集成电路将I2L逻辑与功率达林顿晶体管相结合。大面积离子注入允许在一个衬底上制造低压和高压器件。所得到的集成电路允许通过简单或复杂的控制功能来控制多个负载。

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