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    • 43. 发明授权
    • Rubber composition for base tread and tire
    • 基础胎面和轮胎的橡胶组合物
    • US07919553B2
    • 2011-04-05
    • US12555885
    • 2009-09-09
    • Satoshi KawasakiTakayuki Hattori
    • Satoshi KawasakiTakayuki Hattori
    • C08K5/04C08K5/00
    • C08L7/00B60C1/0016C08K5/098C08L9/00C08L21/00C08L2666/08
    • The present invention aims to produce a rubber composition for a base tread, which suppresses reversion and achieves excellent mechanical strength, fuel economy and processability, and a tire using the rubber composition, with high efficiency to provide them to customers at low prices. The present invention relates to a rubber composition for a base tread, containing: a rubber component; and a mixture of a zinc salt of an aliphatic carboxylic acid and a zinc salt of an aromatic carboxylic acid, wherein the rubber component contains natural rubber and butadiene rubber, the butadiene rubber content being 10 to 90% by mass per 100% by mass of the rubber component, and the mixture of a zinc salt of an aliphatic carboxylic acid and a zinc salt of an aromatic carboxylic acid is contained in an amount of 1 to 10 parts by mass per 100 parts by mass of the rubber component.
    • 本发明的目的在于制造一种用于胎面基底的橡胶组合物,其能够高效率地以低价格向顾客提供逆转和优异的机械强度,燃料经济性和加工性,以及使用该橡胶组合物的轮胎。 本发明涉及一种用于胎面基底的橡胶组合物,其包含:橡胶组分; 和脂肪族羧酸的锌盐与芳香族羧酸的锌盐的混合物,其中,所述橡胶成分含有天然橡胶和丁二烯橡胶,丁二烯橡胶的含量为每100质量%为10〜90质量% 橡胶成分,芳香族羧酸的锌盐和锌盐的混合物的含量相对于橡胶成分为100质量份为1〜10质量份。
    • 44. 发明申请
    • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    • 非易失性半导体存储器件
    • US20090310410A1
    • 2009-12-17
    • US12546062
    • 2009-08-24
    • Yoshihiko KusakabeKenichi OtoSatoshi Kawasaki
    • Yoshihiko KusakabeKenichi OtoSatoshi Kawasaki
    • G11C16/04G11C8/10
    • G11C8/08G11C8/10G11C8/14G11C16/08
    • A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.
    • 对应于每个字线提供的子解码器元件由相同的导电型MOS晶体管构成。 子解码器元件布置在多个列中,使得用于形成子解码器元件的有源区域的布局在Y方向上反转并且沿着X方向被一个子解码器元件移位。 调整副解码器元件的布置,使得高电压不施加到在Y方向上相邻的两个栅电极。 用于形成子解码器元件组的阱区的阱电压被设置为电压电平,使得子解码器元件的晶体管的源极到衬底被设置为深的反向偏置状态。 在非易失性半导体存储器件中,可以抑制在供给正或负高电压的子解码器电路或字线驱动电路中的寄生MOS的泄漏。
    • 45. 发明授权
    • Nonvolatile semiconductor memory device
    • 非易失性半导体存储器件
    • US07596033B2
    • 2009-09-29
    • US12216489
    • 2008-07-07
    • Yoshihiko KusakabeKenichi OtoSatoshi Kawasaki
    • Yoshihiko KusakabeKenichi OtoSatoshi Kawasaki
    • G11C16/06G11C16/04
    • G11C8/08G11C8/10G11C8/14G11C16/08
    • A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.
    • 对应于每个字线提供的子解码器元件由相同的导电型MOS晶体管构成。 子解码器元件布置在多个列中,使得用于形成子解码器元件的有源区域的布局在Y方向上反转并且沿着X方向被一个子解码器元件移位。 调整副解码器元件的布置,使得高电压不施加到在Y方向上相邻的两个栅电极。 用于形成子解码器元件组的阱区的阱电压被设置为电压电平,使得子解码器元件的晶体管的源极到衬底被设置为深的反向偏置状态。 在非易失性半导体存储器件中,可以抑制在供给正或负高电压的子解码器电路或字线驱动电路中的寄生MOS的泄漏。
    • 46. 发明申请
    • Nonvolatile semiconductor memory device
    • 非易失性半导体存储器件
    • US20080273396A1
    • 2008-11-06
    • US12216489
    • 2008-07-07
    • Yoshihiko KusakabeKenichi OtoSatoshi Kawasaki
    • Yoshihiko KusakabeKenichi OtoSatoshi Kawasaki
    • G11C16/04
    • G11C8/08G11C8/10G11C8/14G11C16/08
    • A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.
    • 对应于每个字线提供的子解码器元件由相同的导电型MOS晶体管构成。 子解码器元件布置在多个列中,使得用于形成子解码器元件的有源区域的布局在Y方向上反转并且沿着X方向被一个子解码器元件移位。 调整副解码器元件的布置,使得高电压不施加到在Y方向上相邻的两个栅电极。 用于形成子解码器元件组的阱区的阱电压被设置为电压电平,使得子解码器元件的晶体管的源极到衬底被设置为深的反向偏置状态。 在非易失性半导体存储器件中,可以抑制在供给正或负高电压的子解码器电路或字线驱动电路中的寄生MOS的泄漏。
    • 47. 发明申请
    • Nonvolatile semiconductor memory device
    • 非易失性半导体存储器件
    • US20070183213A1
    • 2007-08-09
    • US11701404
    • 2007-02-02
    • Yoshihiko KusakabeKenichi OtoSatoshi Kawasaki
    • Yoshihiko KusakabeKenichi OtoSatoshi Kawasaki
    • G11C16/06G11C8/00G11C11/34G11C16/04
    • G11C8/08G11C8/10G11C8/14G11C16/08
    • A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.
    • 对应于每个字线提供的子解码器元件由相同的导电型MOS晶体管构成。 子解码器元件布置在多个列中,使得用于形成子解码器元件的有源区域的布局在Y方向上反转并且沿着X方向被一个子解码器元件移位。 调整副解码器元件的布置,使得高电压不施加到在Y方向上相邻的两个栅电极。 用于形成子解码器元件组的阱区的阱电压被设置为电压电平,使得子解码器元件的晶体管的源极到衬底被设置为深的反向偏置状态。 在非易失性半导体存储器件中,可以抑制在供给正或负高电压的子解码器电路或字线驱动电路中的寄生MOS的泄漏。