专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20060262600A1 Non-Volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20060262600A1
公开(公告)日：2006-11-23
申请号：US11492994
申请日：2006-07-26
申请人： Riichiro Shirota , Kikuko Sugimae
发明人： Riichiro Shirota , Kikuko Sugimae
IPC分类号： G11C16/04
CPC分类号： H01L27/11526 , G11C16/0433 , H01L27/105 , H01L27/11521 , H01L27/11529 , H01L27/11558
摘要： A memory cell has a selection transistor constituted of an MOS transistor having a gate electrode and a cell transistor constituted of an MOS transistor having the same polarity as the selection transistor, in such a configuration that these two transistors are connected in series. A bit line is connected to a drain region of the selection transistor and a word line is connected to the gate electrode thereof. A gate electrode of the cell transistor is not electrically connected anywhere so as to be in a floating potential state, while a drain region thereof is connected to a source region of the selection transistor. A source line is connected to a source region of the cell transistor.
摘要翻译：存储单元具有由具有栅电极的MOS晶体管和由与选择晶体管具有相同极性的MOS晶体管构成的单元晶体管构成的选择晶体管，其结构是这两个晶体管串联连接。位线连接到选择晶体管的漏极区域，并且字线连接到其栅电极。单元晶体管的栅极电极不会在任何地方电连接，以便处于浮置电位状态，而其漏极区域连接到选择晶体管的源极区域。源极线连接到单元晶体管的源极区域。

42. 发明授权

US07095651B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07095651B2
公开(公告)日：2006-08-22
申请号：US11211633
申请日：2005-08-26
申请人： Riichiro Shirota , Kikuko Sugimae
发明人： Riichiro Shirota , Kikuko Sugimae
IPC分类号： G11C16/04 , G11C5/06
CPC分类号： H01L27/11526 , G11C16/0433 , H01L27/105 , H01L27/11521 , H01L27/11529 , H01L27/11558
摘要： A memory cell has a selection transistor constituted of an MOS transistor having a gate electrode and a cell transistor constituted of an MOS transistor having the same polarity as the selection transistor, in such a configuration that these two transistors are connected in series. A bit line is connected to a drain region of the selection transistor and a word line is connected to the gate electrode thereof. A gate electrode of the cell transistor is not electrically connected anywhere so as to be in a floating potential state, while a drain region thereof is connected to a source region of the selection transistor. A source line is connected to a source region of the cell transistor.
摘要翻译：存储单元具有由具有栅电极的MOS晶体管和由与选择晶体管具有相同极性的MOS晶体管构成的单元晶体管构成的选择晶体管，其结构是这两个晶体管串联连接。位线连接到选择晶体管的漏极区域，并且字线连接到其栅电极。单元晶体管的栅极电极不会在任何地方电连接，以便处于浮置电位状态，而其漏极区域连接到选择晶体管的源极区域。源极线连接到单元晶体管的源极区域。

43. 发明申请

US20130077461A1 STORAGE DEVICE 审中-公开
标题翻译：储存设备
公开(公告)号：US20130077461A1
公开(公告)日：2013-03-28
申请号：US13423755
申请日：2012-03-19
申请人： Akihiro Koga , Yasushi Tomizawa , Hideo Shinomiya , Moto Yabuki , Jun Hirota , Yoshihisa Iwata , Masayuki Ichige , Kikuko Sugimae , Junya Matsunami
发明人： Akihiro Koga , Yasushi Tomizawa , Hideo Shinomiya , Moto Yabuki , Jun Hirota , Yoshihisa Iwata , Masayuki Ichige , Kikuko Sugimae , Junya Matsunami
IPC分类号： G11B9/00
CPC分类号： G11B9/02 , G11B9/1418 , G11B9/1436
摘要： A storage device includes a recording medium, a probe, a substrate, and a processing unit. The recording medium stores a signal. The probe reads or writes the signal to/from the recording medium. The substrate is provided with the probe via a conductive anchor interposed therebetween and a first connection terminal connected to the probe. The processing unit is provided on the substrate and has a second connection terminal. The second connection terminal is connected to the first connection terminal.
摘要翻译：存储装置包括记录介质，探针，基板和处理单元。记录介质存储信号。探头将信号读取或写入记录介质。基板经由插入其间的导电锚固体和连接到探针的第一连接端子设置有探针。处理单元设置在基板上，并具有第二连接端子。第二连接端子连接到第一连接端子。

44. 发明申请

US20090154214A1 SEMICONDUCTOR MEMORY 有权
标题翻译：半导体存储器
公开(公告)号：US20090154214A1
公开(公告)日：2009-06-18
申请号：US12370638
申请日：2009-02-13
申请人： Kikuko Sugimae , Satoshi Tanaka , Koji Hashimoto , Masayuki Ichige
发明人： Kikuko Sugimae , Satoshi Tanaka , Koji Hashimoto , Masayuki Ichige
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G11C5/063 , G11C16/0408 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531
摘要： Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AAi, AAi, . . . , AAn, which extend on a memory cell array along the column length; a plurality of word line patterns WL1, WL2, . . . , extend along the row length and are non-uniformly arranged; a plurality of select gate line patterns SG1, SG2, . . . , are arranged parallel to the plurality of word line patterns; borderless contacts are formed near the ends of the word line patterns on the memory cell array, and are in contact with part of an interconnect extended from the end of the memory cell array, but are not in contact with interconnects adjacent to that interconnect; and bit line contacts are formed within contact forming regions provided by removing part of the plurality of word line patterns and select gate line patterns through double exposure.
摘要翻译：用于字线的无边界触点或通过位线的触点使用互连图案形成，其中一部分被去除。半导体存储器包括：多个有源区域AAi，AAi，...。。。，AAn，其沿着列长延伸在存储单元阵列上; 多个字线图案WL1，WL2，...。。。沿着行长延伸并且不均匀地布置; 多个选择栅极线图案SG1，SG2，...。。。被平行于所述多个字线图形排列; 在存储单元阵列上的字线图案的端部附近形成无边界触点，并且与从存储单元阵列的端部延伸的互连部分接触，但不与与该互连件相邻的互连件接触; 并且通过去除多个字线图案的一部分而提供的接触形成区域内形成位线接触，并通过双重曝光选择栅极线图案。

45. 发明申请

US20070148973A1 Fabrication of semiconductor device for flash memory with increased select gate width 有权
标题翻译：具有增加选择栅极宽度的闪存半导体器件制造
公开(公告)号：US20070148973A1
公开(公告)日：2007-06-28
申请号：US11319895
申请日：2005-12-28
申请人： Masaaki Higashitani , Tuan Pham , Masayuki Ichige , Koji Hashimoto , Satoshi Tanaka , Kikuko Sugimae
发明人： Masaaki Higashitani , Tuan Pham , Masayuki Ichige , Koji Hashimoto , Satoshi Tanaka , Kikuko Sugimae
IPC分类号： H01L21/302 , B44C1/22 , H01L21/461
CPC分类号： H01L21/28123 , H01L21/32139 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques. In one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size F that are spaced apart by the feature size F, for instance. The second photomask has an opening which is sized to create a desired inter-select gate gap, such as 3 F or 5 F. A third photomask is used to provide protective portions in a second photoresist layer over the select gate structures. The final structure has memory elements of width F spaced apart by a distance F, and select gates of width 3 F spaced apart by 3 F or 5 F. In another approach, the patterns of three photomasks are transferred to respective photoresist layers to create an analogous final structure.
摘要翻译：使用现有的光刻技术制造具有例如45-55nm或更小的通道长度的存储元件的非易失性存储器件。在一种方法中，第一和第二光掩模的图案被转移到相同的光致抗蚀剂层。第一光掩模可以具有例如由特征尺寸F间隔开的具有给定特征尺寸F的开口。第二光掩模具有一个开口，其尺寸被设计成产生期望的选择性间隙，例如3F或5F。第三光掩模用于在选择栅极结构上的第二光致抗蚀剂层中提供保护部分。最终结构具有间隔开距离F的宽度为F的存储元件，并且以3F或5F隔开的宽度3F的选择栅极。另一种方法是将三个光掩模的图案转移到相应的光致抗蚀剂层，以产生类似的最终结构。

46. 发明申请

US20050056869A1 Nonvolatile semiconductor memory cell matrix, a mehtod for operating the same, monolithic integrated circuits and systems 失效
标题翻译：非易失性半导体存储单元矩阵，用于操作相同的单片集成电路和系统
公开(公告)号：US20050056869A1
公开(公告)日：2005-03-17
申请号：US10903015
申请日：2004-08-02
申请人： Masayuki Ichige , Fumitaka Arai , Kikuko Sugimae
发明人： Masayuki Ichige , Fumitaka Arai , Kikuko Sugimae
IPC分类号： G11C16/06 , G11C11/00 , G11C16/02 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/16 , H01L21/8246 , H01L21/8247 , H01L27/00 , H01L27/10 , H01L27/115 , H01L29/74 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , G11C11/005 , G11C16/0483 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a plurality of word lines WL; a plurality of bit lines BL; memory cell transistors having a charge storage layer arranged in the column whose charge storage state is controlled by one of the word lines; memory cell transistor rows MSGm, MSGn functioning as select gate lines by injecting a charge into the charge storage layer of a memory cell transistor to form an enhancement mode transistor. Any one of a first select gate transistor or a second transistor, or both may be formed by a memory cell transistor functioning as a select gate transistor.
摘要翻译：非易失性半导体存储器包括多个字线WL; 多个位线BL; 存储单元晶体管，具有布置在列中的电荷存储层，其电荷存储状态由一条字线控制; 存储单元晶体管行MSGm，MSGn通过将电荷注入到存储单元晶体管的电荷存储层中而用作选择栅极线，以形成增强型晶体管。第一选择晶体管或第二晶体管中的任何一个或两者可以由用作选择栅极晶体管的存储单元晶体管形成。

47. 发明授权

US07847363B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07847363B2
公开(公告)日：2010-12-07
申请号：US12370638
申请日：2009-02-13
申请人： Kikuko Sugimae , Satoshi Tanaka , Koji Hashimoto , Masayuki Ichige
发明人： Kikuko Sugimae , Satoshi Tanaka , Koji Hashimoto , Masayuki Ichige
IPC分类号： G11C5/00
CPC分类号： G11C5/063 , G11C16/0408 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531
摘要： Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AAi, AAi+1, . . . , AAn, which extend on a memory cell array along the column length; a plurality of word line patterns WL1, WL2, . . . , extend along the row length and are non-uniformly arranged; a plurality of select gate line patterns SG1, SG2, . . . , are arranged parallel to the plurality of word line patterns; borderless contacts are formed near the ends of the word line patterns on the memory cell array, and are in contact with part of an interconnect extended from the end of the memory cell array, but are not in contact with interconnects adjacent to that interconnect; and bit line contacts are formed within contact forming regions provided by removing part of the plurality of word line patterns and select gate line patterns through double exposure.
摘要翻译：用于字线的无边界触点或通过位线的触点使用互连图案形成，其中一部分被去除。半导体存储器包括：多个有源区域AAi，AAi + 1，...，。。，AAn，其沿着列长延伸在存储单元阵列上; 多个字线图案WL1，WL2，...。。。沿着行长延伸并且不均匀地布置; 多个选择栅极线图案SG1，SG2，...。。。被平行于所述多个字线图形排列; 在存储单元阵列上的字线图案的端部附近形成无边界触点，并且与从存储单元阵列的端部延伸的互连部分接触，但不与与该互连件相邻的互连件接触; 并且通过去除多个字线图案的一部分而提供的接触形成区域内形成位线接触，并通过双重曝光选择栅极线图案。

48. 发明授权

US07365018B2 Fabrication of semiconductor device for flash memory with increased select gate width 有权
标题翻译：具有增加选择栅极宽度的闪存半导体器件制造
公开(公告)号：US07365018B2
公开(公告)日：2008-04-29
申请号：US11319895
申请日：2005-12-28
申请人： Masaaki Higashitani , Tuan Pham , Masayuki Ichige , Koji Hashimoto , Satoshi Tanaka , Kikuko Sugimae
发明人： Masaaki Higashitani , Tuan Pham , Masayuki Ichige , Koji Hashimoto , Satoshi Tanaka , Kikuko Sugimae
IPC分类号： H01L21/302
CPC分类号： H01L21/28123 , H01L21/32139 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques. In one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size F that are spaced apart by the feature size F, for instance. The second photomask has an opening which is sized to create a desired inter-select gate gap, such as 3 F or 5 F. A third photomask is used to provide protective portions in a second photoresist layer over the select gate structures. The final structure has memory elements of width F spaced apart by a distance F, and select gates of width 3 F spaced apart by 3 F or 5 F. In another approach, the patterns of three photomasks are transferred to respective photoresist layers to create an analogous final structure.
摘要翻译：使用现有的光刻技术制造具有例如45-55nm或更小的通道长度的存储元件的非易失性存储器件。在一种方法中，第一和第二光掩模的图案被转移到相同的光致抗蚀剂层。第一光掩模可以具有例如由特征尺寸F间隔开的具有给定特征尺寸F的开口。第二光掩模具有一个开口，其尺寸被设计成产生期望的选择性间隙，例如3F或5F。第三光掩模用于在选择栅极结构上的第二光致抗蚀剂层中提供保护部分。最终结构具有间隔开距离F的宽度为F的存储元件，并且以3F或5F隔开的宽度3F的选择栅极。另一种方法是将三个光掩模的图案转移到相应的光致抗蚀剂层，以形成类似的最终结构。

49. 发明申请

US20060077702A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20060077702A1
公开(公告)日：2006-04-13
申请号：US11125274
申请日：2005-05-10
申请人： Kikuko Sugimae , Satoshi Tanaka , Koji Hashimoto , Masayuki Ichige
发明人： Kikuko Sugimae , Satoshi Tanaka , Koji Hashimoto , Masayuki Ichige
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C16/0408 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531
摘要： Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AAi, AAi+1, . . . , AAn, which extend on a memory cell array along the column length; a plurality of word line patterns WL1, WL2, . . . , extend along the row length and are non-uniformly arranged; a plurality of select gate line patterns SG1, SG2, . . . , are arranged parallel to the plurality of word line patterns; borderless contacts are formed near the ends of the word line patterns on the memory cell array, and are in contact with part of an interconnect extended from the end of the memory cell array, but are not in contact with interconnects adjacent to that interconnect; and bit line contacts are formed within contact forming regions provided by removing part of the plurality of word line patterns and select gate line patterns through double exposure.
摘要翻译：用于字线的无边界触点或通过位线的触点使用互连图案形成，其中一部分被去除。半导体存储器包括：多个有源区域AA 1，A 2，...，N 1，...，。。，沿着列长延伸在存储单元阵列上的AA 多个字线图形WL 1，WL 2，...。。。沿着行长延伸并且不均匀地布置; 多个选择栅极线图案SG 1，SG 2，...。。。被平行于所述多个字线图形排列; 在存储单元阵列上的字线图案的端部附近形成无边界触点，并且与从存储单元阵列的端部延伸的互连部分接触，但不与与该互连件相邻的互连件接触; 并且通过去除多个字线图案的一部分而提供的接触形成区域内形成位线接触，并通过双重曝光选择栅极线图案。

50. 发明授权

US08093662B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US08093662B2
公开(公告)日：2012-01-10
申请号：US12856850
申请日：2010-08-16
申请人： Kikuko Sugimae , Satoshi Tanaka , Koji Hashimoto , Masayuki Ichige
发明人： Kikuko Sugimae , Satoshi Tanaka , Koji Hashimoto , Masayuki Ichige
IPC分类号： H01L23/58
CPC分类号： G11C5/063 , G11C16/0408 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531
摘要： Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AAi, AAi+1, . . . , AAn, which extend on a memory cell array along the column length; a plurality of word line patterns WL1, WL2, . . . , extend along the row length and are non-uniformly arranged; a plurality of select gate line patterns SG1, SG2, . . . , are arranged parallel to the plurality of word line patterns; borderless contacts are formed near the ends of the word line patterns on the memory cell array, and are in contact with part of an interconnect extended from the end of the memory cell array, but are not in contact with interconnects adjacent to that interconnect; and bit line contacts are formed within contact forming regions provided by removing part of the plurality of word line patterns and select gate line patterns through double exposure.
摘要翻译：用于字线的无边界触点或通过位线的触点使用互连图案形成，其中一部分被去除。半导体存储器包括：多个有源区域AAi，AAi + 1，...，。。，AAn，其沿着列长延伸在存储单元阵列上; 多个字线图案WL1，WL2，...。。。沿着行长延伸并且不均匀地布置; 多个选择栅极线图案SG1，SG2，...。。。被平行于所述多个字线图形排列; 在存储单元阵列上的字线图案的端部附近形成无边界触点，并且与从存储单元阵列的端部延伸的互连部分接触，但不与与该互连件相邻的互连件接触; 并且通过去除多个字线图案的一部分而提供的接触形成区域内形成位线接触，并通过双重曝光选择栅极线图案。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式