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    • 42. 发明授权
    • Semiconductor testing apparatus, semiconductor testing circuit chip, and
probe card
    • 半导体测试仪器,半导体测试电路芯片和探针卡
    • US5666049A
    • 1997-09-09
    • US526216
    • 1995-09-11
    • Toshio YamadaAtsushi FujiwaraMichihiro InoueKazuhiro Matsuyama
    • Toshio YamadaAtsushi FujiwaraMichihiro InoueKazuhiro Matsuyama
    • G01R31/3193G11C29/56G01R31/28
    • G01R31/31935G11C29/56
    • The present invention comprises a plurality of semiconductor testing circuit chips 2 having an exclusive function of testing a plurality of one item of semiconductor integrated-circuit chips 1, a computer 3 for controlling the semiconductor testing circuit chips 2 and for collecting the test results, and a motherboard 4 on which the plurality of chips 1 to be tested and the plurality of testing circuit chips 2 are mounted so that the chips 1 to be tested are connected to the testing circuit chips 2. Since the major testing functions are incorporated into the testing circuit chips 2, the computer 3 for collecting the test results can sufficiently be composed of a low-price computer, so that it is possible to greatly lower the price of the semiconductor testing apparatus. By increasing the number of the testing circuit chips 2, it is possible to greatly increase the number of chips which can be tested simultaneously. Consequently, there can be provided a semiconductor testing apparatus which realizes the reduction in price and the increase in number of the semiconductor integrated circuits tested simultaneously, thereby significantly reducing the cost of testing the semiconductor integrated circuits.
    • 本发明包括具有测试多个半导体集成电路芯片1的独特功能的多个半导体测试电路芯片2,用于控制半导体测试电路芯片2并用于收集测试结果的计算机3,以及 其上安装有待测试的多个芯片1和多个测试电路芯片2的母板4,使得要测试的芯片1连接到测试电路芯片2.由于主要测试功能被并入测试 电路芯片2,用于收集测试结果的计算机3可以充分地由低价计算机构成,从而可以大大降低半导体测试装置的价格。 通过增加测试电路芯片2的数量,可以大大增加可同时测试的芯片的数量。 因此,可以提供一种实现同时测试的半导体集成电路的价格降低和数量增加的半导体测试装置,从而显着降低了半导体集成电路的测试成本。
    • 43. 发明授权
    • Semiconductor testing apparatus, semiconductor testing circuit chip, and
probe card
    • 半导体测试仪器,半导体测试电路芯片和探针卡
    • US5497079A
    • 1996-03-05
    • US113689
    • 1993-08-31
    • Toshio YamadaAtsushi FujiwaraMichihiro InoueKazuhiro Matsuyama
    • Toshio YamadaAtsushi FujiwaraMichihiro InoueKazuhiro Matsuyama
    • G01R31/3193G11C29/56G01R31/28
    • G01R31/31935G11C29/56
    • The present invention comprises a plurality of semiconductor testing circuit chips 2 having an exclusive function of testing a plurality of one item of semiconductor integrated-circuit chips 1, a computer 3 for controlling the semiconductor testing circuit chips 2 and for collecting the test results, and a motherboard 4 on which the plurality of chips 1 to be tested and the plurality of testing circuit chips 2 are mounted so that the chips 1 to be tested are connected to the testing circuit chips 2. Since the major testing functions are incorporated into the testing circuit chips 2, the computer 3 for collecting the test results can sufficiently be composed of a low-price computer, so that it is possible to greatly lower the price of the semiconductor testing apparatus. By increasing the number of the testing circuit chips 2, it is possible to greatly increase the number of chips which can be tested simultaneously. Consequently, there can be provided a semiconductor testing apparatus which realizes the reduction in price and the increase in number of the semiconductor integrated circuits tested simultaneously, thereby significantly reducing the cost of testing the semiconductor integrated circuits.
    • 本发明包括具有测试多个半导体集成电路芯片1的独特功能的多个半导体测试电路芯片2,用于控制半导体测试电路芯片2并用于收集测试结果的计算机3,以及 其上安装有待测试的多个芯片1和多个测试电路芯片2的母板4,使得要测试的芯片1连接到测试电路芯片2.由于主要测试功能被并入测试 电路芯片2,用于收集测试结果的计算机3可以充分地由低价计算机构成,从而可以大大降低半导体测试装置的价格。 通过增加测试电路芯片2的数量,可以大大增加可同时测试的芯片的数量。 因此,可以提供一种实现同时测试的半导体集成电路的价格降低和数量增加的半导体测试装置,从而显着降低了半导体集成电路的测试成本。
    • 48. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US5546346A
    • 1996-08-13
    • US354124
    • 1994-12-06
    • Masashi AgataKazuhiro MatsuyamaHironori AkamatsuHirohito KikukawaAkihiro SawadaShunichi Iwanari
    • Masashi AgataKazuhiro MatsuyamaHironori AkamatsuHirohito KikukawaAkihiro SawadaShunichi Iwanari
    • G11C11/409G11C7/10G11C11/407G11C7/00
    • G11C7/1072
    • In a synchronous DRAM required to be capable of performing high-speed consecutive operations in synchronism with a clock signal, a DBI-line pair is connected between a DQ-line pair and an RDB-line pair, and pipeline operation whose single cycle time is divided into four periods is employed. This S-DRAM has following: a first precharge circuit for precharging or voltage-equalizing the DQ-line pair to a power supply voltage level in the first and forth periods only; a second precharge circuit for voltage-equalizing the DBI-line pair to a ground voltage level in the first and second periods only; a third precharge circuit for voltage-equalizing the RDB-line pair to the power supply voltage level in the first and second periods only; first and second differential amplifiers for transmitting data on the DQ lines onto the DBI lines in the third period and for holding the data on the DBI lines in the fourth period; and a third differential amplifier which transmits the data on the DBI lines onto the RDB lines in the third period and which holds the data on the RDB lines in the fourth period.
    • 在需要与时钟信号同步执行高速连续操作的同步DRAM中,DBI线对连接在DQ线对和RDB线对之间,其流水线操作的单周期时间为 分为四个阶段。 该S-DRAM具有以下:第一预充电电路,用于仅在第一和第四周期中将DQ线对预充电或电压均衡至电源电压电平; 第二预充电电路,用于仅在第一和第二周期中将DBI线对对电压均衡至接地电压电平; 第三预充电电路,用于仅在第一和第二周期中将RDB线对对电压均衡至电源电压电平; 第一和第二差分放大器,用于在第三周期中将DQ线上的数据发送到DBI线上,并且用于在第四周期中将数据保存在DBI线上; 以及第三差分放大器,其在第三周期中将DBI线上的数据发送到RDB线上,并且在第四周期中将数据保存在RDB线上。