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41. 发明授权

US5347492A Semiconductor integrated circuit device 失效
公开(公告)号：US5347492A
公开(公告)日：1994-09-13
申请号：US152387
申请日：1993-11-16
申请人： Masashi Horiguchi , Kiyoo Itoh , Yoshiki Kawajiri , Goro Kitsukawa , Takayuki Kawahara , Takesada Akiba
发明人： Masashi Horiguchi , Kiyoo Itoh , Yoshiki Kawajiri , Goro Kitsukawa , Takayuki Kawahara , Takesada Akiba
IPC分类号： G01R31/317 , G05F3/24 , G11C5/14 , G11C13/00
CPC分类号： G11C5/147 , G01R31/31715 , G05F3/24
摘要： An intermediate voltage generating circuit for generating a voltage lying between an external power supply voltage and a ground voltage, and two voltage limiter circuits for generating internal power supply voltages and stabilized with this intermediate voltage as a reference are provided in a semiconductor integrated circuit. Even if the external power supply voltage or the ground voltage fluctuates, no disagreement is produced between a logical threshold of a circuit operating on the external power supply voltage and a logical threshold of a circuit operating on the internal power supply voltage.

42. 发明授权

US5265055A Semiconductor memory having redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器
公开(公告)号：US5265055A
公开(公告)日：1993-11-23
申请号：US818434
申请日：1991-12-27
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/80 , G11C29/808 , G11C29/781
摘要： A redundancy technique is introduced for a semiconductor memory and, more particularly a redundancy technique for a dynamic random access memory (DRAM) having a storage capacity of 16 mega bits or more. In such a DRAM, the efficiency of the redundancy technique is reduced, since a memory array is divided into a large number of memory mats. According to the present redundancy technique, in a semiconductor memory including a memory array which has a plurality of word lines, a plurality of bit lines arranged so that two-level crossings are formed between the word lines and the bit lines, and memory cells disposed at desired ones of the two-level crossings, there is provided, furthermore, a plurality of spare word (or bit) lines, address comparing circuits for storing therein a defective address existing in the memory array, to compare an address to be accessed with the defective address, and selection circuitry for replacing a word or bit line including a defective memory cell by a spare word (or bit) line in accordance with the result of the comparison. The memory array of the semiconductor memory is divided into M memory mats (where M .gtoreq.2), the number m of word or bit lines which are simultaneously replaced by spare word (or bit) lines, is less than the number M and equal to a divisor thereof, and the number L of spare word (or bit) lines per one memory mat and the number R of address comparing circuits satisfy a relation L
摘要翻译：为半导体存储器引入冗余技术，更具体地说，涉及具有16兆位或更多存储容量的动态随机存取存储器（DRAM）的冗余技术。在这样的DRAM中，冗余技术的效率降低，因为存储器阵列被分成大量的存储器垫。根据本冗余技术，在包括具有多个字线的存储器阵列的半导体存储器中，布置成使得在字线和位线之间形成两级交叉的多个位线，并且设置存储单元此外，在两级交叉口中的期望的一个处，还提供了多个备用字（或位）线，地址比较电路，用于在其中存储存在存储器阵列中的缺陷地址，以将要访问的地址与缺陷地址和用于根据比较结果用备用字（或位）行替换包括有缺陷存储单元的字或位线的选择电路。半导体存储器的存储器阵列被分成M个存储器垫（其中M> / = 2），由备用字（或位）线同时替换的字或位线的数量m小于数M，每个存储器垫的备用字（或位）的数量L和地址比较电路的数量R满足L

43. 发明授权

US4726021A Semiconductor memory having error correcting means 失效
标题翻译：具有误差校正装置的半导体存储器
公开(公告)号：US4726021A
公开(公告)日：1988-02-16
申请号：US853230
申请日：1986-04-17
申请人： Masashi Horiguchi , Masakazu Aoki , Yoshinobu Nakagome , Shinichi Ikenaga , Katsuhiro Shimohigashi
发明人： Masashi Horiguchi , Masakazu Aoki , Yoshinobu Nakagome , Shinichi Ikenaga , Katsuhiro Shimohigashi
IPC分类号： G06F11/10 , G11C29/24 , G01R31/28
CPC分类号： G06F11/1008 , G06F11/1076 , G11C29/24
摘要： A semiconductor memory having an error correcting function is provided, which has a device by which the user finds no difficulty in making use of the semiconductor memory and can test it with ease. In the semiconductor memory, a signal indicative of the completion of the preparation for reading/writing is outputted from the memory so that the user, after detecting the output of this signal, performs reading/writing data. To facilitate tests, such as a memory cell test for a redundant bit (check bit), an encoding circuit test and a decoding circuit test, the present invention provides that the arranged tests can be made independently of each other.
摘要翻译：提供了具有纠错功能的半导体存储器，其具有用户不用利用半导体存储器并且可以容易地进行测试的装置。在半导体存储器中，从存储器输出表示完成读/写准备的信号，使得用户在检测到该信号的输出之后，执行读/写数据。为了便于诸如用于冗余位（校验位）的存储器单元测试，编码电路测试和解码电路测试的测试，本发明提供了可以彼此独立地进行布置的测试。

44. 发明授权

US4701884A Semiconductor memory for serial data access 失效
标题翻译：用于串行数据访问的半导体存储器
公开(公告)号：US4701884A
公开(公告)日：1987-10-20
申请号：US896257
申请日：1986-08-14
申请人： Masakazu Aoki , Masashi Horiguchi , Yoshinobu Nakagome , Shinichi Ikenaga , Katsuhiro Shimohigashi , Toshiaki Masuhara , Kiyoo Itoh , Hideo Nakamura , Osamu Minato
发明人： Masakazu Aoki , Masashi Horiguchi , Yoshinobu Nakagome , Shinichi Ikenaga , Katsuhiro Shimohigashi , Toshiaki Masuhara , Kiyoo Itoh , Hideo Nakamura , Osamu Minato
IPC分类号： G11C11/56 , H01L27/108 , G11C13/00
CPC分类号： G11C11/565 , H01L27/10805
摘要： A semiconductor memory device is proposed wherein at least an array comprising a plurality of memory cells each having at least one capacity, a select mechanism for specifying the position of each memory cell, data lines connected to said memory cells for transmitting the data and a data writing and a data reading mechanisms are provided. The feature of this device lies in that the voltage generator for serially generating three or more values of the voltage which are different from each other and the means for applying said voltage to said memory cells are provided on the same semiconductor board as the same said memory cells, and as the said reading mechanism the column register is provided which, as said reading mechanism, has the mechanism for deciding the data, transfer gate which is provided between said deciding means and said data line, and the bias charge transfer mechanism which is provided between said transfer gate and said deciding mechanism, and having at least two or more memory elements for temporarily storing said decided data.
摘要翻译：提出了一种半导体存储器件，其中至少包括多个具有至少一个容量的存储单元的阵列，用于指定每个存储单元的位置的选择机构，连接到所述存储器单元的用于发送数据的数据线和数据提供写入和数据读取机制。该装置的特征在于，用于串联产生彼此不同的三个或更多个电压值的电压发生器和用于将所述电压施加到所述存储单元的装置设置在与所述存储器相同的半导体板上并且作为所述读取机构，列寄存器被提供，其作为所述读取机构具有用于确定数据的机制，所述决定装置和所述数据线之间提供的传送门和作为所述读取机构的偏置电荷传送机构提供在所述传送门和所述判定机构之间，并且具有用于临时存储所述决定的数据的至少两个或更多个存储器元件。

45. 发明授权

US08264893B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08264893B2
公开(公告)日：2012-09-11
申请号：US13238114
申请日：2011-09-21
申请人： Binhaku Taruishi , Hiroki Miyashita , Ken Shibata , Masashi Horiguchi
发明人： Binhaku Taruishi , Hiroki Miyashita , Ken Shibata , Masashi Horiguchi
IPC分类号： G11C7/00
CPC分类号： G11C7/1084 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/1096
摘要： A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.
摘要翻译：在对存储器单元进行的写入操作的指令的接收之后，数据输入缓冲器从非活动状态改变为活动状态。输入缓冲器是具有例如基于SSTL的接口规格的差分输入缓冲器，其通过接通电源开关而使其通过电流流动并接收信号而进入激活状态，同时紧随着小的变化小振幅信号。由于只有当提供了对存储器单元的写操作指令时，输入缓冲器才进入活动状态，所以在提供指令之前预先使输入缓冲器无效，从而减少浪费的功耗。在另一方面，通过在从写入命令发布到下一个命令发布的时间段内从主动状态变为非活动状态来降低功耗。

46. 发明授权

US08085566B2 Semiconductor circuit device and data processing system 有权
公开(公告)号：US08085566B2
公开(公告)日：2011-12-27
申请号：US12926516
申请日：2010-11-23
申请人： Masashi Horiguchi , Mitsuru Hiraki
发明人： Masashi Horiguchi , Mitsuru Hiraki
IPC分类号： H02M1/00 , H02M3/06 , G05F1/40
CPC分类号： G05F3/242 , H01L2224/16145 , H01L2224/32245 , H01L2224/48137 , H01L2224/4826 , H01L2224/73215 , Y10T307/76 , H01L2924/00
摘要： Occurrence of power supply noise arising in connection with a step-down action at the time of turning on power supply is to be restrained. A step-down unit is provided with a switched capacitor type step-down circuit and a series regulator type step-down circuit, and stepped-down voltage output terminals of the step-down circuits are connected in common. The common connection of the stepped-down voltage output terminals of both step-down circuits makes possible parallel driving of both, selective driving of either or consecutive driving of the two. In the consecutive driving, even if the switched capacitor type step-down circuit is driven after driving the series regulator type step-down circuit first to supply a stepped-down voltage to loads, the switched capacitor type step-down circuit will need only to be compensated for a discharge due to the loads, and a peak of a charge current for capacitors can be kept low. When operation of the switched capacitor type step-down circuit is started, no large rush current arises, and occurrence of noise is restrained.

47. 发明申请

US20100149883A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100149883A1
公开(公告)日：2010-06-17
申请号：US12710394
申请日：2010-02-23
申请人： Binhaku Taruishi , Hiroki Miyashita , Ken Shibata , Masashi Horiguchi
发明人： Binhaku Taruishi , Hiroki Miyashita , Ken Shibata , Masashi Horiguchi
IPC分类号： G11C7/10 , G11C8/18 , G11C7/00 , G11C7/02
CPC分类号： G11C7/1084 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/1096
摘要： In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.
摘要翻译：在具有能够向每个存储单元输入写入数据的数据输入缓冲器的半导体器件中，在接收到对存储器单元进行的写入操作的指令之后，数据输入缓冲器从非活动状态改变为有效状态。数据输入缓冲器是具有例如基于SSTL的接口规格的差分输入缓冲器，其通过接通电源开关而进入活动状态，从而使通过电流流过并在其中立即接收信号小振幅信号的小变化。由于只有在提供了写入操作对存储器单元的指令的情况下，输入缓冲器才进入活动状态，所以在提供写入操作的指令之前，预先使数据输入缓冲器无效，从而减少浪费的功耗。在另一方面，通过在从写入命令发布到下一个命令发布的时间段内从主动状态变为非活动状态来降低功耗。

48. 发明授权

US07667485B2 Semiconductor integrated circuits with power reduction mechanism 失效
标题翻译：半导体集成电路具有功率降低机制
公开(公告)号：US07667485B2
公开(公告)日：2010-02-23
申请号：US12133969
申请日：2008-06-05
申请人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： H03K19/003 , H03K17/16
CPC分类号： H03K19/0016 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , H03K19/00361
摘要： A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.
摘要翻译：包括第一和第二电力线的半导体器件，以及耦合在电力线之间的第一和第二电路块。第一开关元件插入在第一电路块和至少一个电源线之间，并且第二开关元件插入在第二电路块和至少一个电源线之间。第一开关元件被导通以允许第一电路块通过第一和第二电力线接收电力电压，而第二开关元件变得不导通，以防止第二电路块通过第一和第二电力接收电力电压使得流过第二电路的漏电流被抑制。

49. 发明申请

US20080273413A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080273413A1
公开(公告)日：2008-11-06
申请号：US12165681
申请日：2008-07-01
申请人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
发明人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C5/14 , G11C5/147 , G11C7/1072 , G11C8/12 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.
摘要翻译：提供了一种同步DRAM，其包括基于DRAM是否处于掉电模式的电源电路的操作的布置。在一个实施例中，提供了第一电源电路和第二电源电路，其接收外部提供的电压并输出内部电源电压。当同步DRAM的半导体器件处于掉电模式时，第一电源电路不工作。然而，第二电源电路在掉电模式期间连续运行。在另一种布置中，基于DRAM是否处于断电模式来控制限压器电路的操作。

50. 发明申请

US20080072085A1 Semiconductor integrated circuit device having power reduction mechanism 失效
标题翻译：具有降压机构的半导体集成电路装置
公开(公告)号：US20080072085A1
公开(公告)日：2008-03-20
申请号：US11979100
申请日：2007-10-31
申请人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
发明人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
IPC分类号： G06F1/32
CPC分类号： H01L27/0207 , G06F1/3203 , G11C5/14 , H01L27/0218 , H03K3/356113 , H03K19/0013 , H03K19/0016 , H03K19/01721
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
摘要翻译：半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。逻辑门连接到第一电势点和第二电位点。半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值逻辑门。该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

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