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41. 发明授权

US07410855B2 Semiconductor device 有权
公开(公告)号：US07410855B2
公开(公告)日：2008-08-12
申请号：US11841841
申请日：2007-08-20
申请人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
发明人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

42. 发明授权

US07391085B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07391085B2
公开(公告)日：2008-06-24
申请号：US11299773
申请日：2005-12-13
申请人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
发明人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
IPC分类号： H01L27/092
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
摘要翻译：半导体器件包括半导体衬底，形成在衬底上的nMISFET，nMISFET包括形成在衬底上的第一电介质和形成在第一电介质上的第一金属栅极，并由选自Ti，Zr，Hf， Ta，Sc，Y，镧系元素和锕系和选自所述一种金属元素的硼化物，硅化物和锗化合物的一种，以及形成在所述衬底上的pMISFET，所述pMISFET包括形成在所述衬底上的第二电介质和第二金属栅电极形成在第二电介质上并由与第一金属栅电极相同的材料制成，第二电介质面向第二金属栅电极的至少一部分由绝缘材料制成，绝缘材料与至少一部分的第一电介质面向第一金属栅电极。

43. 发明申请

US20080128822A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080128822A1
公开(公告)日：2008-06-05
申请号：US11753186
申请日：2007-05-24
申请人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
发明人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L21/28097 , H01L21/823842 , H01L21/823857 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm−3 or more to 1×1022 cm−3 or less.
摘要翻译：半导体器件包括：p沟道MIS晶体管，包括：第一绝缘层，形成在源极区域和漏极区域之间的半导体区域上，并且至少包含硅和氧; 形成在所述第一绝缘层上并且包含铪，硅，氧和氮的第二绝缘层，以及形成在所述第二绝缘层上的第一栅电极。第一和第二绝缘层分别具有第一和第二区域。第一和第二区域在从第一绝缘层和第二绝缘层之间的界面的膜厚度方向上为0.3nm的范围内。第一和第二区域中的每一个包括浓度为1×10 20 cm -3或更多至1×10 22 cm -3的铝原子， 3 以下。

44. 发明申请

US20070145493A1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070145493A1
公开(公告)日：2007-06-28
申请号：US11635040
申请日：2006-12-07
申请人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
发明人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
IPC分类号： H01L29/76
CPC分类号： H01L21/823842
摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.
摘要翻译：半导体器件包括衬底，形成在衬底上的n型阱上的p沟道MIS晶体管，具有形成在其上并由Ta-C合金形成的第一栅极电介质和第一栅电极，其中晶体取向比例膜厚方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]的TaC（111）面为80％以上，n型沟道MIS晶体管形成在p- 在基板上良好地形成具有形成在其上的第二栅极电介质和第二栅电极，并且由TaC（111）在膜厚度方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]为60％以下。

45. 发明授权

US08410556B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08410556B2
公开(公告)日：2013-04-02
申请号：US13290552
申请日：2011-11-07
申请人： Reika Ichihara , Masato Koyama
发明人： Reika Ichihara , Masato Koyama
IPC分类号： H01L29/78 , H01L29/43
CPC分类号： H01L27/092 , H01L21/823842 , H01L29/4966 , H01L29/518 , H01L29/6659
摘要： A semiconductor device includes pMISFET and nMIS formed on the semiconductor substrate. The pMISFET includes, on the semiconductor substrate, first source/drain regions, a first gate dielectric formed therebetween, first lower and upper metal layers stacked on the first gate dielectric, a first upper metal layer containing at least one metallic element belonging to groups IIA and IIIA. The nMISFET includes, on the semiconductor substrate, second source/drain regions, second gate dielectric formed therebetween, a second lower and upper metal layers stacked on the second gate dielectric and the second upper metal layer substantially having the same composition as the first upper metal layer. The first lower metal layer is thicker than the second lower metal layer, and the atomic density of the metallic element contained in the first gate dielectric is lower than the atomic density of the metallic element contained in the second gate dielectric.
摘要翻译：半导体器件包括在半导体衬底上形成的pMISFET和nMIS。 pMISFET在半导体衬底上包括第一源极/漏极区域，在其间形成的第一栅极电介质，堆叠在第一栅极电介质上的第一下部和上部金属层，包含至少一个属于IIA族金属元素的第一上部金属层和IIIA。 nMISFET在半导体衬底上包括第二源极/漏极区域，在其间形成的第二栅极电介质，堆叠在第二栅极电介质上的第二下部和上部金属层，以及基本上具有与第一上部金属相同的组成的第二上部金属层层。第一下金属层比第二下金属层厚，并且包含在第一栅极电介质中的金属元素的原子密度低于包含在第二栅极电介质中的金属元素的原子密度。

46. 发明申请

US20090267159A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090267159A1
公开(公告)日：2009-10-29
申请号：US12388965
申请日：2009-02-19
申请人： Kosuke Tstsumura , Masakazu Goto , Reika Ichihara , Masato Koyama , Shigeru Kawanaka , Kazuaki Nakajima
发明人： Kosuke Tstsumura , Masakazu Goto , Reika Ichihara , Masato Koyama , Shigeru Kawanaka , Kazuaki Nakajima
IPC分类号： H01L27/092
CPC分类号： H01L21/823828 , H01L21/823842 , H01L29/785
摘要： A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate dielectric formed on the substrate and a first gate electrode layer formed on the first dielectric, and an n-channel MIS transistor formed on the substrate, the n-channel transistor having a second gate dielectric formed on the substrate and a second gate electrode layer formed on the second dielectric. A bottom layer of the first gate electrode layer in contact with the first gate dielectric and a bottom layer of the second gate electrode layer in contact with the second gate dielectric have the same orientation and the same composition including Ta and C, and a mole ratio of Ta to a total of C and Ta, (Ta/(Ta+C)), is larger than 0.5.
摘要翻译：半导体器件包括半导体衬底，形成在衬底上的p沟道MIS晶体管，形成在衬底上的第一栅极电介质的p沟道晶体管和形成在第一电介质上的第一栅极电极层，以及n沟道形成在衬底上的MIS晶体管，所述n沟道晶体管具有形成在衬底上的第二栅极电介质和形成在第二电介质上的第二栅极电极层。与第一栅极电介质接触的第一栅极电极层的底层和与第二栅极电介质接触的第二栅电极层的底层具有相同的取向和相同的组成，包括Ta和C，以及摩尔比的Ta与总计C和Ta（Ta /（Ta + C））大于0.5。

47. 发明授权

US08355275B2 Resistance change memory 有权
标题翻译：电阻变化记忆
公开(公告)号：US08355275B2
公开(公告)日：2013-01-15
申请号：US13239899
申请日：2011-09-22
申请人： Reika Ichihara , Akira Takashima
发明人： Reika Ichihara , Akira Takashima
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/003 , G11C2213/76
摘要： According to one embodiment, a resistance change memory includes a memory cell including a resistance change element and a stacked layer structure which are connected in series, a control circuit configured to control a first operation of changing the resistance change element from a first resistance value to a second resistance value lower than the first resistance value, and a voltage pulse generating circuit configured to generate a first voltage pulse to be applied to the memory cell in the first operation. The stacked layer structure includes two conductive layers and an insulating layer formed between the two conductive layers. Amplitude of the first voltage pulse is in a first voltage area in which the stacked layer structure functions as a capacitor. The first voltage pulse satisfies Ron×C
摘要翻译：根据一个实施例，电阻变化存储器包括：串联连接的包括电阻变化元件和堆叠层结构的存储单元;控制电路，被配置为控制将电阻变化元件从第一电阻值改变到第二电阻值低于第一电阻值;以及电压脉冲发生电路，被配置为在第一操作中产生要施加到存储单元的第一电压脉冲。堆叠层结构包括两个导电层和形成在两个导电层之间的绝缘层。第一电压脉冲的振幅在第一电压区域中，其中堆叠层结构用作电容器。第一电压脉冲满足Ron×C

48. 发明授权

US08076732B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08076732B2
公开(公告)日：2011-12-13
申请号：US12491728
申请日：2009-06-25
申请人： Reika Ichihara , Masato Koyama
发明人： Reika Ichihara , Masato Koyama
IPC分类号： H01L21/8238
CPC分类号： H01L27/092 , H01L21/823842 , H01L29/4966 , H01L29/518 , H01L29/6659
摘要： A semiconductor device includes pMISFET and nMIS formed on the semiconductor substrate. The pMISFET includes, on the semiconductor substrate, first source/drain regions, a first gate dielectric formed therebetween, first lower and upper metal layers stacked on the first gate dielectric, a first upper metal layer containing at least one metallic element belonging to groups IIA and IIIA. The nMISFET includes, on the semiconductor substrate, second source/drain regions, second gate dielectric formed therebetween, a second lower and upper metal layers stacked on the second gate dielectric and the second upper metal layer substantially having the same composition as the first upper metal layer. The first lower metal layer is thicker than the second lower metal layer, and the atomic density of the metallic element contained in the first gate dielectric is lower than the atomic density of the metallic element contained in the second gate dielectric.
摘要翻译：半导体器件包括在半导体衬底上形成的pMISFET和nMIS。 pMISFET在半导体衬底上包括第一源极/漏极区域，在其间形成的第一栅极电介质，堆叠在第一栅极电介质上的第一下部和上部金属层，包含至少一种属于IIA族金属元素的第一上部金属层和IIIA。 nMISFET在半导体衬底上包括第二源极/漏极区域，在其间形成的第二栅极电介质，堆叠在第二栅极电介质上的第二下部和上部金属层，以及基本上具有与第一上部金属相同的组成的第二上部金属层层。第一下金属层比第二下金属层厚，并且包含在第一栅极电介质中的金属元素的原子密度低于包含在第二栅极电介质中的金属元素的原子密度。

49. 发明申请

US20090321844A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090321844A1
公开(公告)日：2009-12-31
申请号：US12491728
申请日：2009-06-25
申请人： Reika Ichihara , Masato Koyama
发明人： Reika Ichihara , Masato Koyama
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/823842 , H01L29/4966 , H01L29/518 , H01L29/6659
摘要： A semiconductor device includes pMISFET and nMIS formed on the semiconductor substrate. The pMISFET includes, on the semiconductor substrate, first source/drain regions, a first gate dielectric formed therebetween, first lower and upper metal layers stacked on the first gate dielectric, a first upper metal layer containing at least one metallic element belonging to groups IIA and IIIA. The nMISFET includes, on the semiconductor substrate, second source/drain regions, second gate dielectric formed therebetween, a second lower and upper metal layers stacked on the second gate dielectric and the second upper metal layer substantially having the same composition as the first upper metal layer. The first lower metal layer is thicker than the second lower metal layer, and the atomic density of the metallic element contained in the first gate dielectric is lower than the atomic density of the metallic element contained in the second gate dielectric.
摘要翻译：半导体器件包括在半导体衬底上形成的pMISFET和nMIS。 pMISFET在半导体衬底上包括第一源极/漏极区域，在其间形成的第一栅极电介质，堆叠在第一栅极电介质上的第一下部和上部金属层，包含至少一个属于IIA族金属元素的第一上部金属层和IIIA。 nMISFET在半导体衬底上包括第二源极/漏极区域，在其间形成的第二栅极电介质，堆叠在第二栅极电介质上的第二下部和上部金属层，以及基本上具有与第一上部金属相同的组成的第二上部金属层层。第一下金属层比第二下金属层厚，并且包含在第一栅极电介质中的金属元素的原子密度低于包含在第二栅极电介质中的金属元素的原子密度。

50. 发明授权

US08331137B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08331137B2
公开(公告)日：2012-12-11
申请号：US13234796
申请日：2011-09-16
申请人： Akira Takashima , Reika Ichihara
发明人： Akira Takashima , Reika Ichihara
IPC分类号： G11C11/00
CPC分类号： G11C11/5685 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C13/0097 , G11C2013/0092 , G11C2213/33 , G11C2213/76
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell includes a variable resistance element and a capacitor connected in series between first and second conductive lines, and a control circuit applying one of first and second voltage pulses to the memory cell. The capacitor is charged by a leading edge of one of the first and second voltage pulses, and discharged a trailing edge of one of the first and second voltage pulses. The control circuit makes waveforms of the trailing edges of the first and second voltage pulses be different, changes a resistance value of the variable resistance element from a first resistance value to a second resistance value by using the first voltage pulse, and changes the resistance value of the variable resistance element from the second resistance value to the first resistance value by using the second voltage pulse.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括存储单元，其包括可变电阻元件和串联连接在第一和第二导线之间的电容器，以及将第一和第二电压脉冲之一施加到存储单元的控制电路。电容器由第一和第二电压脉冲之一的前沿充电，并且将第一和第二电压脉冲之一的后沿放电。控制电路使得第一和第二电压脉冲的后沿的波形不同，通过使用第一电压脉冲将可变电阻元件的电阻值从第一电阻值改变为第二电阻值，并且改变电阻值通过使用第二电压脉冲从第二电阻值到第一电阻值。

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