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    • 43. 发明授权
    • Polishing machine
    • 抛光机
    • US4593495A
    • 1986-06-10
    • US674663
    • 1984-11-26
    • Hideo KawakamiShinichi TazawaMasami Endo
    • Hideo KawakamiShinichi TazawaMasami Endo
    • B24B37/10B24B7/17
    • B24B37/105
    • A polishing machine for polishing the surfaces of the workpieces to be processed has upper and lower surface plates which are rotated relative to each other. A plurality of carriers are placed between the upper and lower surface plates and each of the carriers has a plurality of bores into which the workpieces are fitted. These carriers are engaged with both the sun gear and the internal ring gear within the same plane. In account of the sun gear and the internal ring gear, the carriers are rotated round the sun gear, turning round their own axes. The internal ring gear can be lifted up and down by a lift mechanism. The sun gear is slidably attached to a hollow driving shaft and has a feed screw which is engaged with a feed nut. This feed nut is rotatably fitted onto the hollow driving shaft in such a way that the nut is limited of its movement in the axial direction. The sun gear can be lifted up and down independently of the internal ring gear when an operating means including the feed screw and nut is operated.
    • 用于抛光待处理工件表面的抛光机具有相对于彼此旋转的上表面板和下表面板。 多个载体被放置在上表面板和下表面板之间,并且每个载体具有多个孔,工件被安装在该孔中。 这些载体在同一平面内与太阳齿轮和内齿圈啮合。 由于太阳齿轮和内齿圈,托架绕着太阳齿轮旋转,转动自己的轴线。 内齿圈可以通过提升机构上下升降。 太阳齿轮可滑动地附接到中空的驱动轴上并具有与进给螺母啮合的进给螺杆。 该进给螺母可旋转地装配到中空驱动轴上,使得螺母在轴向方向上的运动受到限制。 当包括进给螺杆和螺母在内的操作装置工作时,太阳齿轮可独立于内齿圈上下升降。
    • 45. 发明授权
    • Inverter circuit, power converter circuit, and electric vehicle
    • 逆变电路,电源转换电路和电动车
    • US08780598B2
    • 2014-07-15
    • US13192885
    • 2011-07-28
    • Masami Endo
    • Masami Endo
    • H02M7/5387
    • H02M7/5387B60L15/007H02M7/53871Y02T10/645
    • An object is to reduce, with the control circuit of the full-bridge inverter circuit, distortions in an output signal of the inverter circuit resulting from an error in control of the switching of the high-side transistors and low-side transistors included in the first half-bridge circuit and the second half-bridge circuit. The pulse width of a signal that controls ON/OFF of the high-side transistors and low-side transistors included in the first half-bridge circuit and the second half-bridge circuit is reduced, i.e., the duty cycle of the signal is reduced. This results in a reduction in short-circuit periods during which both the high-side transistor and the low-side transistor are on, thereby reducing distortions in a signal.
    • 目的是通过全桥逆变器电路的控制电路来减少逆变器电路的输出信号的失真,这是由于控制包括在内部的高侧晶体管和低侧晶体管的低侧晶体管的开关导致的误差 第一半桥电路和第二半桥电路。 控制包括在第一半桥电路和第二半桥电路中的高侧晶体管和低侧晶体管的ON / OFF的信号的脉冲宽度减小,即信号的占空比减小 。 这导致高侧晶体管和低侧晶体管导通的短路周期的减少,从而减少信号中的失真。
    • 47. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US08630110B2
    • 2014-01-14
    • US13459566
    • 2012-04-30
    • Masami Endo
    • Masami Endo
    • G11C11/24
    • G11C14/0054G06F12/0895G06F2212/1028H01L21/84H01L27/1203Y02D10/13Y02P70/605
    • The semiconductor memory device includes: a memory circuit including a transistor including an oxide semiconductor in a semiconductor layer; a capacitor for storing electric charge for reading data retained in the memory circuit; a charge storage circuit for controlling storage of electric charge in the capacitor; a data detection circuit for controlling data reading; a timing control circuit for generating a first signal controlling storage of electric charge in the capacitor (storage is conducted with the charge storage circuit, and the first signal is generated with a second signal at a supply voltage and a third signal delayed from the second signal at the supply voltage in a period immediately after the supply of the supply voltage); an inverter circuit for outputting a potential obtained by inverting a potential of one electrode of the capacitor.
    • 半导体存储器件包括:存储电路,包括在半导体层中包括氧化物半导体的晶体管; 用于存储用于读取存储在电路中的数据的电荷的电容器; 用于控制电容器中的电荷存储的电荷存储电路; 用于控制数据读取的数据检测电路; 定时控制电路,用于产生控制电容器中的电荷存储的第一信号(存储器与电荷存储电路一起进行,第一信号以第二信号以电源电压产生,第三信号从第二信号延迟 在电源电压供给之后的电源电压下); 用于输出通过反转电容器的一个电极的电位而获得的电位的反相器电路。
    • 49. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE
    • 半导体存储器件
    • US20120281456A1
    • 2012-11-08
    • US13459566
    • 2012-04-30
    • Masami Endo
    • Masami Endo
    • G11C11/24
    • G11C14/0054G06F12/0895G06F2212/1028H01L21/84H01L27/1203Y02D10/13Y02P70/605
    • The semiconductor memory device includes: a memory circuit including a transistor including an oxide semiconductor in a semiconductor layer; a capacitor for storing electric charge for reading data retained in the memory circuit; a charge storage circuit for controlling storage of electric charge in the capacitor; a data detection circuit for controlling data reading; a timing control circuit for generating a first signal controlling storage of electric charge in the capacitor (storage is conducted with the charge storage circuit, and the first signal is generated with a second signal at a supply voltage and a third signal delayed from the second signal at the supply voltage in a period immediately after the supply of the supply voltage); an inverter circuit for outputting a potential obtained by inverting a potential of one electrode of the capacitor.
    • 半导体存储器件包括:存储电路,包括在半导体层中包括氧化物半导体的晶体管; 用于存储用于读取存储在电路中的数据的电荷的电容器; 用于控制电容器中的电荷存储的电荷存储电路; 用于控制数据读取的数据检测电路; 定时控制电路,用于产生控制电容器中的电荷存储的第一信号(存储器与电荷存储电路一起进行,并且第一信号以供给电压的第二信号和从第二信号延迟的第三信号产生) 在电源电压供给之后的电源电压下); 用于输出通过反转电容器的一个电极的电位而获得的电位的反相器电路。
    • 50. 发明申请
    • INTEGRATED CIRCUIT, METHOD FOR DRIVING THE SAME, AND SEMICONDUCTOR DEVICE
    • 集成电路,驱动它们的方法和半导体器件
    • US20120140550A1
    • 2012-06-07
    • US13307060
    • 2011-11-30
    • Masami EndoTakuro Ohmaru
    • Masami EndoTakuro Ohmaru
    • G11C11/24G11C11/00
    • H03K3/356008H03K3/012H03K21/023H03K21/403
    • An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop.
    • 提供一种可以切换到静止状态并且可以从静止状态快速返回的集成电路。 提供一种能够在不降低运行速度的情况下降低功耗的集成电路。 提供了一种用于驱动集成电路的方法。 集成电路包括第一触发器和包括非易失性存储器电路的第二触发器。 在提供电力的操作状态下,第一触发器保持数据。 在停止供电的静止状态下,第二触发器保持数据。 在从操作状态转变到静止状态时,数据从第一触发器传送到第二触发器。 从静止状态返回到工作状态时,数据从第二触发器传送到第一触发器。