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41. 发明授权

US5703831A Synchronous semiconductor memory device having internal circuitry enabled only when commands are applied in normal sequence 失效
标题翻译：只有当按照正常顺序应用命令时，内部电路才能使能同步半导体存储器件
公开(公告)号：US5703831A
公开(公告)日：1997-12-30
申请号：US768081
申请日：1996-12-16
申请人： Seiji Sawada
发明人： Seiji Sawada
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/403 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1072
摘要： In a synchronous semiconductor memory device in which contents of an internal operation is designated by commands applied in synchronization with a clock signal, operations of decoding read, write and precharge commands different from an active command for activating the internal operation are enabled only when the active command is active. Even if a command such as read command other than the active command is applied during an inactive state of internal circuits, other command decoder cannot perform the decoding, so that unnecessary circuit operation can be prevented.
摘要翻译：在通过与时钟信号同步的命令指定内部操作的内容的同步半导体存储器件中，只有在激活内部操作的激活命令的活动命令中解码读取，写入和预充电命令的操作不同的操作才能被激活命令激活。即使在内部电路的非活动状态期间应用诸如有效命令之类的读命令的命令，其他命令解码器也不能执行解码，从而可以防止不必要的电路操作。

42. 发明授权

US5465063A Pulse generating circuit with temperature compensation 失效
标题翻译：具有温度补偿的脉冲发生电路
公开(公告)号：US5465063A
公开(公告)日：1995-11-07
申请号：US49398
申请日：1993-04-21
申请人： Tatsuya Fukuda , Shigeru Mori , Masanori Hayashikoshi , Seiji Sawada
发明人： Tatsuya Fukuda , Shigeru Mori , Masanori Hayashikoshi , Seiji Sawada
IPC分类号： G11C5/14 , G11C7/22 , G11C11/406 , H03K3/03 , H03K3/354 , H03L1/02
CPC分类号： G11C11/40626 , G11C11/406 , G11C5/147 , G11C7/22 , H03K3/0315
摘要： A pulse signal generating circuit includes a ring oscillator and an internal voltage generating circuit. The internal voltage generating circuit generates an internal voltage depending on an operation temperature. The internal voltage is low at a normal temperature, and is high at a high temperature. Each inverter in the ring oscillator is driven by the internal voltage supplied from the internal voltage generating circuit. Thereby, a period of a pulse signal increases at a normal temperature, and decreases at a high temperature.
摘要翻译：脉冲信号发生电路包括环形振荡器和内部电压产生电路。内部电压产生电路根据操作温度产生内部电压。内部电压在正常温度下为低电平，在高温下为高电平。环形振荡器中的每个反相器由内部电压产生电路提供的内部电压驱动。因此，脉冲信号的周期在正常温度下增加，并且在高温下降低。

43. 发明申请

US20090091997A1 SEMICONDUCTOR MEMORY DEVICE SUITABLE FOR MOUNTING ON PORTABLE TERMINAL 有权
标题翻译：适用于便携式终端安装的半导体存储器件
公开(公告)号：US20090091997A1
公开(公告)日：2009-04-09
申请号：US12333913
申请日：2008-12-12
申请人： Takeo Miki , Seiji Sawada , Masaki TSUKUDE
发明人： Takeo Miki , Seiji Sawada , Masaki TSUKUDE
IPC分类号： G11C11/401 , G11C7/22
CPC分类号： G11C11/406 , G11C8/18 , G11C11/40615 , G11C2211/4061
摘要： A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register.
摘要翻译：触发产生电路提供触发信号。延迟电路接收触发信号，并提供通过延迟触发信号而产生的延迟信号。时钟计数器接收时钟，对从接收到触发信号到接收延迟信号的时间段中的接收时钟进行计数，并提供计数结果。确定电路存储时钟数和等待时间之间的关系，并且确定与从时钟计数器提供的计数结果相对应的等待时间。延迟寄存器保存所确定的延迟。 WAIT控制电路根据等待时间寄存器中保存的等待时间外部提供WAIT信号。

44. 发明授权

US07480200B2 Semiconductor memory device suitable for mounting on portable terminal 有权
标题翻译：适用于便携式终端的半导体存储器件
公开(公告)号：US07480200B2
公开(公告)日：2009-01-20
申请号：US12007032
申请日：2008-01-04
申请人： Seiji Sawada
发明人： Seiji Sawada
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C8/18 , G11C11/40615 , G11C2211/4061
摘要： A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register.
摘要翻译：触发产生电路提供触发信号。延迟电路接收触发信号，并提供通过延迟触发信号而产生的延迟信号。时钟计数器接收时钟，对从接收到触发信号到接收延迟信号一段时间的接收时钟进行计数，并提供计数结果。确定电路存储时钟数和等待时间之间的关系，并且确定与从时钟计数器提供的计数结果相对应的等待时间。延迟寄存器保存所确定的延迟。 WAIT控制电路根据等待时间寄存器中保存的等待时间外部提供WAIT信号。

45. 发明授权

US07035366B2 Delay locked loop circuit and its control method 失效
公开(公告)号：US07035366B2
公开(公告)日：2006-04-25
申请号：US10166123
申请日：2002-06-11
申请人： Hiroto Tokutome , Seiji Sawada
发明人： Hiroto Tokutome , Seiji Sawada
IPC分类号： H04L7/00 , H03D3/24 , H03L7/06 , H03L7/00
CPC分类号： G11C7/222 , G11C7/22 , H03L7/0814 , H03L7/087 , H03L7/091
摘要： A delay locked loop (DLL) circuit comprising: a fundamental phase comparator for detecting a fundamental phase difference of two input signals; a delay circuit; a delay control circuit for adjusting a delay time of the delay circuit in response to an output signal of the fundamental phase comparator; and at least one further phase comparator for detecting a phase difference other than the fundamental phase difference such that an amount of change of the delay time is changed in accordance with the fundamental phase difference.

46. 发明授权

US06426900B1 Synchronous semiconductor memory device performing data output in synchronization with external clock 失效
标题翻译：同步半导体存储器件与外部时钟同步执行数据输出
公开(公告)号：US06426900B1
公开(公告)日：2002-07-30
申请号：US09907589
申请日：2001-07-19
申请人： Yukiko Maruyama , Seiji Sawada
发明人： Yukiko Maruyama , Seiji Sawada
IPC分类号： G11C700
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1072 , G11C7/222 , H03K2005/00071 , H03L7/0814 , H03L7/089
摘要： A DLL circuit generates a control clock specifying an operating timing of a data output buffer according to an external clock. The DLL circuit includes a replica delay time adjusting section and a phase control section. The phase control section controls such that a feedback clock and the external clock becomes in phase. The replica delay time adjusting section adjusts a delay time of the feedback clock behind the control clock according to an operating condition serving as a factor for changing a processing time of the data output buffer.
摘要翻译： DLL电路根据外部时钟产生指定数据输出缓冲器的操作定时的控制时钟。 DLL电路包括复制延迟时间调整部分和相位控制部分。相位控制部分控制使得反馈时钟和外部时钟变为同相。复制延迟时间调整部根据用作改变数据输出缓冲器的处理时间的因素的操作条件来调整控制时钟后面的反馈时钟的延迟时间。

47. 发明授权

US06335887B1 Semiconductor memory device allowing switching of word configuration 失效
公开(公告)号：US06335887B1
公开(公告)日：2002-01-01
申请号：US09727544
申请日：2000-12-04
申请人： Shigekazu Aoki , Seiji Sawada , Mikio Asakura , Takeshi Hamamoto , Masakazu Hirose
发明人： Shigekazu Aoki , Seiji Sawada , Mikio Asakura , Takeshi Hamamoto , Masakazu Hirose
IPC分类号： G11C700
CPC分类号： G11C29/34
摘要： The semiconductor memory device has a word configuration determination signal generating circuit including a plurality of generating circuits, each of which is formed of two clocked inverters and two inverters. In a normal operation mode, a test mode signal TX4 is inactivated and a word configuration determination signal [x16E] of an H level is output. In a test mode, the test mode signal TX4 is activated and a word configuration determination signal [x4E] of an H level is output. Thus, in the test mode, the word configuration is switched to the one that is smaller than in the normal operation mode. This allows simultaneous testing of a larger number of semiconductor memory devices.

48. 发明授权

US5893925A Synchronous semiconductor memory device in which burst counter is commonly employed for data writing and for data reading 失效
标题翻译：同步半导体存储器件，其中脉冲串长度计数器通常用于数据写入和数据读取
公开(公告)号：US5893925A
公开(公告)日：1999-04-13
申请号：US767775
申请日：1996-12-17
申请人： Seiji Sawada
发明人： Seiji Sawada
IPC分类号： G11C11/413 , G11C7/10 , G11C11/407 , G11C11/409 , G06F12/00
CPC分类号： G11C7/1072
摘要： A read control flip-flop circuit is activated upon activation of an internal readout instruction signal from a command decoder to generate a signal for activating an internal data reading circuit. A write control flip-flop circuit activates an internal data writing circuit in response to an internal write operation instruction signal from the command decoder. When one of the internal write instruction signal and the internal readout instruction signal from this command decoder is activated, a burst length counter counts a predetermined number of clock cycles, and when the counted value reaches a predetermined value, a reset signal is activated to reset the read control flip-flop circuit and the write control flip-flop circuit. Thus, the layout area of the control portion for internal data read operation and internal data write operation in a synchronous semiconductor memory device is reduced.
摘要翻译：读取控制触发器电路在激活来自命令解码器的内部读出指令信号时产生用于激活内部数据读取电路的信号。写控制触发器电路响应于来自命令解码器的内部写操作指令信号而激活内部数据写入电路。当内部写入指令信号和来自该命令解码器的内部读取指令信号中的一个被激活时，突发长度计数器对预定数量的时钟周期进行计数，当计数值达到预定值时，复位信号被激活以复位读控制触发电路和写控制触发电路。因此，同步半导体存储器件中的用于内部数据读取操作的控制部分和内部数据写入操作的布局面积减小。

49. 发明授权

US5818768A Operation mode setting circuit in semiconductor device 失效
标题翻译：半导体器件中的工作模式设定电路
公开(公告)号：US5818768A
公开(公告)日：1998-10-06
申请号：US767496
申请日：1996-12-16
申请人： Seiji Sawada , Yasuhiro Konishi
发明人： Seiji Sawada , Yasuhiro Konishi
IPC分类号： G11C11/401 , G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1045
摘要： A correspondence defining circuit changes a correspondence between an external signal and an internal signal and supplies it to a mode designating signal generating circuit according to a logic state of an operation mode switching signal. The mode designating signal generating circuit activates a mode designating signal which designates a specific operation mode in a semiconductor device when the internal signal satisfies a prescribed condition. An operation mode setting circuit, applicable to applications in which states of external signals are different without a change of its internal structure, is thus provided.
摘要翻译：对应定义电路改变外部信号和内部信号之间的对应关系，并根据操作模式切换信号的逻辑状态将其提供给模式指定信号发生电路。当内部信号满足规定条件时，模式指定信号发生电路激活指定半导体器件中的特定操作模式的模式指定信号。因此，提供了适用于其外部信号的状态不同而不改变其内部结构的应用的操作模式设定电路。

50. 发明授权

US5815462A Synchronous semiconductor memory device and synchronous memory module 失效
标题翻译：同步半导体存储器件和同步存储器模块
公开(公告)号：US5815462A
公开(公告)日：1998-09-29
申请号：US800905
申请日：1997-02-12
申请人： Yasuhiro Konishi , Hisashi Iwamoto , Takashi Araki , Yasumitsu Murai , Seiji Sawada
发明人： Yasuhiro Konishi , Hisashi Iwamoto , Takashi Araki , Yasumitsu Murai , Seiji Sawada
IPC分类号： G11C11/407 , G06F12/00 , G06F13/16 , G11C7/10 , G11C7/22 , G11C11/409 , G11C8/00
CPC分类号： G11C7/225 , G11C7/1039 , G11C7/1072 , G11C7/22
摘要： A first clock signal for controlling the inputting of an external signal and for controlling internal operation and a second clock signal for controlling data output are applied to separate clock input nodes, respectively. Data output timing with respect to the first clock signal can be adjusted and thus clock access time and data hold time can be adjusted. Internal data read path is pipelined to include a first transfer gate responsive to the first clock signal for transferring internal read data and a second transfer gate responsive to the second clock signal for transferring the internal read data from the first transfer gate for external outputting through an output buffer. A synchronous semiconductor memory device is provided capable of setting clock access time and data hold time at the optimal values depending on the application and of reducing the clock access time.
摘要翻译：用于控制外部信号的输入和用于控制内部操作的第一时钟信号和用于控制数据输出的第二时钟信号分别被施加到分离的时钟输入节点。可以调整相对于第一时钟信号的数据输出定时，从而可以调整时钟存取时间和数据保持时间。内部数据读取路径被流水线化以包括响应于第一时钟信号的第一传送门，用于传送内部读取数据和第二传送门，响应于第二时钟信号，用于从第一传送门传送内部读取数据，以便通过输出缓冲区。提供一种同步半导体存储器件，其能够根据应用和减少时钟存取时间将时钟访问时间和数据保持时间设置在最佳值。

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