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41. 发明授权

US08019974B2 Pipeline processor with write control and validity flags for controlling write-back of execution result data stored in pipeline buffer register 有权
标题翻译：具有写入控制和有效性标志的管道处理器，用于控制存储在流水线缓冲寄存器中的执行结果数据的写入
公开(公告)号：US08019974B2
公开(公告)日：2011-09-13
申请号：US12352154
申请日：2009-01-12
申请人： Jun Tanabe
发明人： Jun Tanabe
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/3826
摘要： A bypass circuit is provided in a pipeline processor. A pipeline register is provided between an instruction execution stage and a write-back stage. The pipeline register stores a data validity flag and a WRITE control flag to control writing data into a general purpose register unit. The data retained in the pipeline register is allowed to be written back into the general purpose register unit when the WRITE control flag indicates “valid”. The pipeline register continues to retain the retained data even after the writing of the retained data into the general purpose register unit. The first pipeline register supplies the retained data to the second stage through the bypass circuit at the time of executing a subsequent instruction having data dependency on a preceding instruction.
摘要翻译：旁路电路设置在流水线处理器中。在指令执行阶段和回写阶段之间提供流水线寄存器。流水线寄存器存储数据有效性标志和写入控制标志，以控制将数据写入通用寄存器单元。当WRITE控制标志指示“有效”时，保留在流水线寄存器中的数据被允许写入通用寄存器单元。即使在将保留的数据写入通用寄存器单元之后，流水线寄存器继续保留保留的数据。第一流水线寄存器在执行具有与先前指令有数据依赖关系的后续指令时，通过旁路电路向第二级提供保留数据。

42. 发明授权

US07917566B2 Arithmetic device capable of obtaining high-accuracy calculation results 失效
标题翻译：能够获得高精度计算结果的算术装置
公开(公告)号：US07917566B2
公开(公告)日：2011-03-29
申请号：US11870173
申请日：2007-10-10
申请人： Jun Tanabe
发明人： Jun Tanabe
IPC分类号： G06F7/38
CPC分类号： G06F9/30014 , G06F9/30036
摘要： A plurality of general-purpose registers each has a first bit width. A computing unit has a first and a second input end, at least the first input end having a second bit width wider than the first bit width, and performs an arithmetical operation on data supplied from the general-purpose registers to the first and second input ends. An overflow register having a bit width narrower than the first bit width holds data on figures overflowed as a result of calculation by the computing unit as overflow data and supplies the held overflow data as higher-order bits to at least one input end of the computing unit.
摘要翻译：多个通用寄存器各自具有第一位宽度。计算单元具有第一和第二输入端，至少第一输入端具有比第一位宽宽的第二位宽，并且对从通用寄存器提供给第一和第二输入的数据执行算术运算结束。具有比第一位宽窄的位宽的溢出寄存器保存作为计算单元作为溢出数据的计算结果溢出的数据上的数据，并将保持的溢出数据作为高位位提供给计算的至少一个输入端单元。

43. 发明申请

US20100063203A1 COATING COMPOSITION 审中-公开
标题翻译：涂料组合物
公开(公告)号：US20100063203A1
公开(公告)日：2010-03-11
申请号：US12447691
申请日：2007-11-01
申请人： Tadahisa Sato , Hideki Maeta , Jun Tanabe , Hirokazu Kyota
发明人： Tadahisa Sato , Hideki Maeta , Jun Tanabe , Hirokazu Kyota
IPC分类号： C09D167/00 , C04B16/00
CPC分类号： C09B67/0098 , C08L33/00 , C09B67/0008 , C09B67/0014 , C09B67/009 , C09D4/00 , C09D5/36 , C09D7/41 , C09D7/65 , C09D7/67
摘要： A coating composition containing a build-up organic pigment fine-particle.
摘要翻译：含有积累有机颜料微粒的涂料组合物。

44. 发明申请

US20060236001A1 Direct memory access controller 审中-公开
标题翻译：直接内存访问控制器
公开(公告)号：US20060236001A1
公开(公告)日：2006-10-19
申请号：US11190184
申请日：2005-07-27
申请人： Jun Tanabe
发明人： Jun Tanabe
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： a transfer control unit issues commands that the transfer data is divided into portions each having a prescribed transfer unit size. The portions of transfer data are sent separately to the device associated with the transfer destination address in such a manner that the final portion of the data to be transferred is transferred using a transfer method that requires a response from the device associated with the data transfer destination address. All other portions of the data to be transferred are transferred using a transfer method that does not require a response from the device associated with the data transfer destination.
摘要翻译：传送控制单元发出传送数据被分割成具有规定的传送单元大小的部分的命令。转移数据的部分被分别发送到与传送目的地地址相关联的设备，使得要传送的数据的最后部分使用需要来自与数据传送目的地相关联的设备的响应的传送方法传送地址。要传输的数据的所有其他部分使用不需要来自与数据传送目的地相关联的设备的响应的传送方法传送。

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