专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20070001222A1 Single transistor memory cell with reduced recombination rates 失效
标题翻译：具有降低复合率的单晶体管存储单元
公开(公告)号：US20070001222A1
公开(公告)日：2007-01-04
申请号：US11172569
申请日：2005-06-30
申请人： Marius Orlowski , James Burnett
发明人： Marius Orlowski , James Burnett
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L29/7841 , H01L29/78687
摘要： A semiconductor fabrication method includes forming a semiconductor structure including source/drain regions disposed on either side of a channel body wherein the source/drain regions include a first semiconductor material and wherein the channel body includes a migration barrier of a second semiconductor material. A gate dielectric overlies the semiconductor structure and a gate module overlies the gate dielectric. An offset in the majority carrier potential energy level between the first and second semiconductor materials creates a potential well for majority carriers in the channel body. The migration barrier may be a layer of the second semiconductor material over a first layer of the first semiconductor material and under a capping layer of the first semiconductor material. In a one dimensional migration barrier, the migration barrier extends laterally through the source/drain regions while, in a two dimensional barrier, the barrier terminates laterally at boundaries defined by the gate module.
摘要翻译：半导体制造方法包括形成半导体结构，该半导体结构包括设置在沟道体两侧的源极/漏极区，其中源极/漏极区包括第一半导体材料，并且其中沟道主体包括第二半导体材料的迁移势垒。栅极电介质覆盖半导体结构，并且栅极模块覆盖在栅极电介质上。在第一和第二半导体材料之间的多数载流子势能级中的偏移对于通道体中的多数载流子产生潜在的井。迁移障碍物可以是第一半导体材料的第一层上的第二半导体材料层和第一半导体材料的覆盖层之下的层。在一维迁移屏障中，迁移屏障横向延伸穿过源极/漏极区域，而在二维屏障中，屏障在由栅极模块限定的边界处横向终止。

42. 发明申请

US20060286736A1 Method for forming an electronic device 有权
标题翻译：电子设备的形成方法
公开(公告)号：US20060286736A1
公开(公告)日：2006-12-21
申请号：US11152931
申请日：2005-06-15
申请人： Marius Orlowski , Brian Goolsby
发明人： Marius Orlowski , Brian Goolsby
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823418
摘要： An electronic device is formed by forming a first and second layer overlying a plurality of transistor locations. An etch is performed to remove portions of the first and second layers to expose a portion of the plurality of transistor locations, while other portions of the first and second layer remain to protect other transistor locations. Subsequently, source/drain locations of the exposed transistor locations are etched along with the remaining portion of the second layer. The etch is substantially terminated by removing the portion of the second layer using an end-point detection technique involving the first layer. Subsequently an epitaxial layer is formed in the source/drain recesses to provide stress on a channel region of the transistor locations.
摘要翻译：通过形成覆盖多个晶体管位置的第一和第二层来形成电子器件。执行蚀刻以去除第一层和第二层的部分以暴露多个晶体管位置的一部分，而第一层和第二层的其它部分保留以保护其他晶体管位置。随后，暴露的晶体管位置的源极/漏极位置与第二层的剩余部分一起被蚀刻。通过使用涉及第一层的端点检测技术去除第二层的部分来基本上终止蚀刻。随后在源极/漏极凹槽中形成外延层，以在晶体管位置的沟道区上提供应力。

43. 发明申请

US20060240629A1 Self correcting suppression of threshold voltage variation in fully depleted transistors 有权
标题翻译：完全耗尽晶体管中阈值电压变化的自校正抑制
公开(公告)号：US20060240629A1
公开(公告)日：2006-10-26
申请号：US11113589
申请日：2005-04-25
申请人： Marius Orlowski , Yasuhito Shiho
发明人： Marius Orlowski , Yasuhito Shiho
IPC分类号： H01L21/336
CPC分类号： H01L27/1203 , H01L21/76283 , H01L29/78603
摘要： A semiconductor fabrication method includes implanting or otherwise introducing a counter doping impurity distribution into a semiconductor top layer of a silicon-on-insulator (SOI) wafer. The top layer has a variable thickness including a first thickness at a first region and a second thickness, greater than the first, at a second region. The impurity distribution is introduced into the top layer such that the net charge deposited in the semiconductor top layer varies linearly with the thickness variation. The counter doping causes the total net charge in the first region to be approximately equal to the net charge in the second region. This variation in deposited net charge leads to a uniform threshold voltage for fully depleted transistors. Fully depleted transistors are then formed in the top layer.
摘要翻译：半导体制造方法包括将反掺杂杂质分布注入或以其它方式引入到绝缘体上硅（SOI）晶片的半导体顶层中。顶层具有包括在第一区域处的第一厚度和大于第一区域的第二厚度的可变厚度。杂质分布被引入到顶层中，使得沉积在半导体顶层中的净电荷随着厚度变化而线性变化。反掺杂导致第一区域中的总净电荷近似等于第二区域中的净电荷。沉积的净电荷的这种变化导致用于完全耗尽的晶体管的均匀阈值电压。然后在顶层中形成完全耗尽的晶体管。

44. 发明申请

US20060068542A1 Isolation trench perimeter implant for threshold voltage control 有权
标题翻译：隔离沟槽周边植入用于阈值电压控制
公开(公告)号：US20060068542A1
公开(公告)日：2006-03-30
申请号：US10955658
申请日：2004-09-30
申请人： Marius Orlowski , James Burnett
发明人： Marius Orlowski , James Burnett
IPC分类号： H01L21/8238
CPC分类号： H01L21/823878 , H01L21/76237
摘要： A method of forming isolation trenches in a semiconductor fabrication process to reduce transistor channel edge effect currents includes forming a masking structure overlying a substrate to expose a first area of the substrate. Spacers are formed on sidewalls of the masking structure. The spacers cover a perimeter region of the first area thereby leaving a second smaller area exposed. The region underlying the second area is etched to form an isolation trench that is then filled with a dielectric. The spacers are removed to expose the perimeter region. Using the masking structure and the trench dielectric as a mask, an impurity distribution is implanted into a portion of the substrate underlying the perimeter region. The impurity distribution thus surrounds a perimeter of the trench dielectric proximal to an upper surface of the substrate. The perimeter impurity distribution dopant, in a typical case, is p-type for NMOS transistors and n-type for PMOS.
摘要翻译：在半导体制造工艺中形成隔离沟槽以减少晶体管沟道边缘效应电流的方法包括形成覆盖衬底的掩模结构以暴露衬底的第一区域。隔板形成在掩蔽结构的侧壁上。间隔物覆盖第一区域的周边区域，从而留下暴露的第二较小区域。蚀刻第二区域下面的区域以形成隔离沟槽，然后填充电介质。去除间隔物以露出周边区域。使用掩模结构和沟槽电介质作为掩模，杂质分布被注入在周边区域下面的衬底的一部分中。因此，杂质分布围绕靠近衬底的上表面的沟槽电介质的周边。在典型情况下，周边杂质分布掺杂剂对于NMOS晶体管为p型，对于PMOS为n型。

45. 发明申请

US20060063392A1 Deposition and patterning of boron nitride nanotube ILD 有权
标题翻译：氮化硼纳米管的沉积和图案ILD
公开(公告)号：US20060063392A1
公开(公告)日：2006-03-23
申请号：US10945319
申请日：2004-09-20
申请人： Peter Ventzek , Kurt Junker , Marius Orlowski
发明人： Peter Ventzek , Kurt Junker , Marius Orlowski
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02112 , B82Y10/00 , H01L21/02282 , H01L21/318 , H01L21/76801 , H01L21/76813 , H01L21/76819 , H01L21/7682 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a dielectric layer is disclosed herein. In accordance with the method, a first material is provided (303) which comprises a suspension of nanoparticles in a liquid medium. A dielectric layer is then formed (305) on the substrate from the suspension through an evaporative process.
摘要翻译：本文公开了形成电介质层的方法。根据该方法，提供第一材料（303），其包括纳米颗粒在液体介质中的悬浮液。然后通过蒸发过程从悬浮液在基底上形成介电层（305）。

46. 发明申请

US20050260816A1 Method for removing a semiconductor layer 失效
标题翻译：去除半导体层的方法
公开(公告)号：US20050260816A1
公开(公告)日：2005-11-24
申请号：US10851607
申请日：2004-05-21
申请人： Marius Orlowski
发明人： Marius Orlowski
IPC分类号： H01L21/336 , H01L27/10 , H01L29/786
CPC分类号： H01L29/78639 , H01L29/42392 , H01L29/66772
摘要： A method of forming a semiconductor device includes forming a first layer over a semiconductor substrate and forming a second layer over the first layer. The second layer includes silicon and has an etch selectivity to the second layer that is greater than approximately 1,000. In one embodiment, the second layer is a porous material, such as porous silicon, porous silicon germanium, porous silicon carbide, and porous silicon carbon alloy. A gate insulator is formed over the second layer and a control electrode is formed over the gate insulator. The first layer is selectively removed with respect to the second layer and the semiconductor substrate.
摘要翻译：形成半导体器件的方法包括在半导体衬底上形成第一层并在第一层上形成第二层。第二层包括硅，并且对第二层具有大于约1,000的蚀刻选择性。在一个实施方案中，第二层是多孔材料，例如多孔硅，多孔硅锗，多孔碳化硅和多孔硅碳合金。在第二层上形成栅极绝缘体，并且在栅极绝缘体上形成控制电极。相对于第二层和半导体衬底选择性地去除第一层。

47. 发明申请

US20050167650A1 Transistor having multiple channels 有权
标题翻译：具有多个通道的晶体管
公开(公告)号：US20050167650A1
公开(公告)日：2005-08-04
申请号：US11091980
申请日：2005-03-29
申请人： Marius Orlowski , Leo Mathew
发明人： Marius Orlowski , Leo Mathew
IPC分类号： H01L21/336 , H01L29/423 , H01L29/786 , H01L29/417
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66772 , H01L29/66795 , H01L29/78654
摘要： A transistor (10) overlies a substrate (12) and has a plurality of overlying channels (72, 74, 76) that are formed in a stacked arrangement. A continuous gate (60) material surrounds each of the channels. Each of the channels is coupled to source and drain electrodes (S/D) to provide increased channel surface area in a same area that a single channel structure is conventionally implemented. A vertical channel dimension between two regions of the gate (60) are controlled by a growth process as opposed to lithographical or spacer formation techniques. The gate is adjacent all sides of the multiple overlying channels. Each channel is formed by growth from a common seed layer and the source and drain electrodes and the channels are formed of a substantially homogenous crystal lattice.
摘要翻译：晶体管（10）覆盖在衬底（12）上并且具有以堆叠布置形成的多个覆盖通道（72,74,76）。连续的门（60）材料围绕每个通道。每个通道耦合到源极和漏极（S / D），以在通常实现单通道结构的相同区域中提供增加的沟道表面积。栅极（60）的两个区域之间的垂直沟道尺寸由生长过程控制，而不是光刻或间隔物形成技术。门与多个上覆通道的所有侧相邻。每个通道由普通种子层生长形成，源极和漏极以及通道由基本均匀的晶格形成。

48. 发明授权

US5605855A Process for fabricating a graded-channel MOS device 失效
标题翻译：用于制造渐变通道MOS器件的工艺
公开(公告)号：US5605855A
公开(公告)日：1997-02-25
申请号：US395339
申请日：1995-02-28
申请人： Ko-Min Chang , Marius Orlowski , Craig Swift , Shih-Wei Sun , Shiang-Chyong Luo
发明人： Ko-Min Chang , Marius Orlowski , Craig Swift , Shih-Wei Sun , Shiang-Chyong Luo
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L29/10 , H01L21/8234
CPC分类号： H01L29/66583 , H01L21/2652 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/66553
摘要： A process for fabricating a graded-channel MOS device includes the formation of a masking layer (16) on the surface of a semiconductor substrate (10) and separated from the surface by a gate oxide layer (12). A first doped region (22) is formed in a channel region (20) of the semiconductor substrate (10) using the masking layer (16) as a doping mask. A second doped region (24) is formed in the channel region (20) and extends from the principal surface (14) of the semiconductor substrate (10) to the first doped region (22). A gate electrode (34) is formed within an opening (18) in the masking layer (16) and aligned to the channel region (20). Upon removal of the masking layer (16) source and drain regions (36, 38) are formed in the semiconductor substrate (10) and aligned to the gate electrode (34).
摘要翻译：用于制造渐变沟道MOS器件的工艺包括在半导体衬底（10）的表面上形成掩模层（16），并通过栅氧化层（12）从表面分离。使用掩模层（16）作为掺杂掩模，在半导体衬底（10）的沟道区（20）中形成第一掺杂区（22）。第二掺杂区域（24）形成在沟道区域（20）中并且从半导体衬底（10）的主表面（14）延伸到第一掺杂区域（22）。栅极电极（34）形成在掩模层（16）的开口（18）内，并与沟道区域（20）对准。在去除掩模层（16）时，源极和漏极区（36,38）形成在半导体衬底（10）中并与栅电极（34）对齐。

49. 发明授权

US5567958A High-performance thin-film transistor and SRAM memory cell 失效
标题翻译：高性能薄膜晶体管和SRAM存储单元
公开(公告)号：US5567958A
公开(公告)日：1996-10-22
申请号：US452944
申请日：1995-05-31
申请人： Marius Orlowski , James D. Hayden , Bich-Yen Nguyen
发明人： Marius Orlowski , James D. Hayden , Bich-Yen Nguyen
IPC分类号： H01L21/336 , H01L27/11 , H01L29/786 , H01L29/78
CPC分类号： H01L27/1108 , H01L29/66757 , H01L29/78696 , Y10S257/903
摘要： A thin-film transistor and SRAM memory cell include thin-film source and drain regions (12, 14) separated by an opening (22) and overlying and insulating layer (11). A thin-film channel layer (16) overlies the thin-film source and drain regions (12, 14) and a portion of the insulating layer (11) exposed by the opening (22). A thin-film gate electrode (20) is positioned in the opening (22) and defines a thin-film channel region (24) in the thin-film channel layer (16). The thin-film gate electrode (20) is separated from the thin-film channel region (24) by a gate dielectric layer (18). The thin-film channel region (24) extends along vertical wall surfaces (26, 28) of the thin-film source and drain regions (12, 14) providing an extended channel length for the thin-film transistor.
摘要翻译：薄膜晶体管和SRAM存储单元包括由开口（22）和上覆绝缘层（11）分开的薄膜源区和漏区（12,14）。薄膜通道层（16）覆盖薄膜源区和漏区（12,14），绝缘层（11）的一部分由开口（22）露出。薄膜栅电极（20）位于开口（22）中并且在薄膜通道层（16）中限定薄膜通道区（24）。薄膜栅电极（20）通过栅介质层（18）与薄膜沟道区（24）分离。薄膜通道区域（24）沿薄膜源极和漏极区域（12,14）的垂直壁表面（26,28）延伸，为薄膜晶体管提供延长的沟道长度。

50. 发明授权

US5235203A Insulated gate field effect transistor having vertically layered elevated source/drain structure 失效
标题翻译：绝缘栅场效应晶体管具有垂直分层的源极/漏极结构
公开(公告)号：US5235203A
公开(公告)日：1993-08-10
申请号：US722416
申请日：1991-06-27
申请人： Carlos Mazure , Marius Orlowski , Matthew S. Noell
发明人： Carlos Mazure , Marius Orlowski , Matthew S. Noell
IPC分类号： H01L29/08
CPC分类号： H01L29/0847
摘要： An insulated gate field effect transistor having a vertically layered elevated source/drain structure includes an electrically conductive suppression region for resistance to hot carrier injection. The device includes a semiconductor substrate of first conductivity type having a gate insulator disposed on the surface of that substrate. A gate electrode, in turn, is disposed on the gate insulator. A lightly doped drain region of second conductivity type is formed in the substrate in alignment with the gate electrode. An electrically conductive suppression region having a first low electrical conductivity is positioned to electrically contact the drain region, but is electrically isolated from the gate electrode and is spaced a first distance from the gate electrode. A heavily doped drain contact also contacts the drain region and is spaced further away from the gate electrode than is the electrically conducted suppression region.
摘要翻译：具有垂直分层的升高的源/漏结构的绝缘栅场效应晶体管包括用于耐热载流子注入的导电抑制区。该器件包括第一导电类型的半导体衬底，其具有设置在该衬底表面上的栅极绝缘体。栅电极依次设置在栅极绝缘体上。第二导电类型的轻掺杂漏极区域与栅电极对准地形成在衬底中。具有第一低导电性的导电抑制区被定位成与漏极区电接触，但是与栅电极电隔离并且与栅电极隔开第一距离。重掺杂的漏极接触还接触漏极区，并且与导电抑制区相比更远离栅电极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式