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41. 发明授权

US08144499B2 Variable resistance memory device 有权
标题翻译：可变电阻存储器件
公开(公告)号：US08144499B2
公开(公告)日：2012-03-27
申请号：US12654484
申请日：2009-12-22
申请人： Makoto Kitagawa , Tsunenori Shiimoto , Wataru Otsuka
发明人： Makoto Kitagawa , Tsunenori Shiimoto , Wataru Otsuka
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0009 , G11C11/56 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2213/11 , G11C2213/33 , G11C2213/34 , G11C2213/56 , G11C2213/79
摘要： A variable resistance memory device includes: a first common line; a second common line; plural memory cells each formed by serially connecting a memory element, resistance of which changes according to applied voltage, and an access transistor between the second common line and the first common line; a common line pass transistor connected between the first common line and a supply node for predetermined voltage; and a driving circuit that controls voltage of the second common line, the predetermined voltage, and voltage of a control node of the common line pass transistor and drives the memory cells.
摘要翻译：可变电阻存储器件包括：第一公共线; 第二条共同线每个存储单元通过串联连接存储元件，其电阻根据施加的电压而变化，以及第二公共线与第一公共线之间的存取晶体管，连接在第一公共线和供电节点之间的公共线路传输晶体管用于预定电压; 以及驱动电路，其控制公共线路通过晶体管的控制节点的第二公共线的电压，预定电压和电压，并驱动存储单元。

42. 发明申请

US20110116296A1 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110116296A1
公开(公告)日：2011-05-19
申请号：US12926118
申请日：2010-10-27
申请人： Makoto Kitagawa , Tsunenori Shiimoto
发明人： Makoto Kitagawa , Tsunenori Shiimoto
IPC分类号： G11C7/08 , G11C5/02
CPC分类号： G11C16/28 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C16/32 , G11C2013/0054 , G11C2013/0073
摘要： A non-volatile semiconductor memory device includes: a memory component in which an electric charge discharging rate between two electrodes is different in accordance with logic of stored information; a sense amplifier that detects the logic of the information by comparing a discharge electric potential of a wiring to which one of the electrodes of the memory component is connected with a reference electric potential; and a load capacitance changing unit that changes load capacitance of a sense node of the sense amplifier to which the discharge electric potential is input or both the load capacitance of the sense node and load capacitance of a reference node of the sense amplifier to which the reference electric potential is input in accordance with the logic of the information read out by the memory component.
摘要翻译：非易失性半导体存储器件包括：存储器组件，其中两个电极之间的电荷放电速率根据存储的信息的逻辑而不同; 读出放大器，通过将存储器部件的一个电极与参考电位相连的布线的放电电位进行比较来检测信息的逻辑; 以及负载电容改变单元，其改变输入放电电位的读出放大器的感测节点的负载电容或感测节点的负载电容以及读出放大器的参考节点的负载电容根据由存储器组件读出的信息的逻辑输入电位。

43. 发明申请

US20110110142A1 Memory device and method of reading memory device 失效
标题翻译：存储器件和读取存储器件的方法
公开(公告)号：US20110110142A1
公开(公告)日：2011-05-12
申请号：US12923978
申请日：2010-10-19
申请人： Makoto Kitagawa , Tsunenori Shiimoto , Hiroshi Yoshihara
发明人： Makoto Kitagawa , Tsunenori Shiimoto , Hiroshi Yoshihara
IPC分类号： G11C7/08 , G11C11/21
CPC分类号： G11C13/004 , G11C13/0007 , G11C13/0061 , G11C2013/0054 , G11C2213/11 , G11C2213/56 , G11C2213/79
摘要： A memory device includes: a memory unit in which an electric charge discharging rate between two electrodes is different in accordance with logic of stored information; a sense amplifier that detects the logic of the information by comparing a discharge electric potential of a wiring to which one electrode of the memory unit is connected with a reference electric potential; and a replica circuit that has a replica unit emulating the memory unit and controls a sense timing of the sense amplifier in accordance with a discharge rate of the replica unit.
摘要翻译：存储装置包括：存储单元，其中两个电极之间的电荷放电速率根据所存储信息的逻辑而不同; 读出放大器，通过将存储单元的一个电极与其连接的布线的放电电位与参考电位进行比较来检测信息的逻辑; 以及复制电路，其具有仿真存储器单元的复制单元，并且根据复制单元的放电速率来控制读出放大器的感测时序。

44. 发明申请

US20100271861A1 VARIABLE-RESISTANCE MEMORY DEVICE AND ITS OPERATION METHOD 有权
标题翻译：可变电阻存储器件及其操作方法
公开(公告)号：US20100271861A1
公开(公告)日：2010-10-28
申请号：US12760262
申请日：2010-04-14
申请人： Makoto Kitagawa
发明人： Makoto Kitagawa
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C13/0009 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0092 , G11C2213/11 , G11C2213/34 , G11C2213/56 , G11C2213/79
摘要： A variable-resistance memory device includes: memory cells; first wires; a second wire; a drive/control section; and a sense amplifier.
摘要翻译：可变电阻存储器件包括：存储器单元; 第一根线第二根线驱动/控制部分; 和一个读出放大器。

45. 发明申请

US20090086537A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20090086537A1
公开(公告)日：2009-04-02
申请号：US12232046
申请日：2008-09-10
申请人： Makoto Kitagawa
发明人： Makoto Kitagawa
IPC分类号： G11C11/39
CPC分类号： G11C11/39
摘要： A semiconductor device, includes a memory cell including a thyristor element with a gate having a pnpn structure formed on a semiconductor substrate and having first and second terminals, and an access transistor formed on the semiconductor substrate and having first and second terminals connected to a bit line and the first terminal of the thyristor element, respectively, and a control section including a load current element whose load current flows, upon reading out operation, to the second terminal side of the thyristor element and configured to carry out access control to the memory cell.
摘要翻译：一种半导体器件，包括：具有晶闸管元件的存储单元，所述晶闸管元件具有形成在半导体衬底上的具有pnpn结构的栅极并具有第一和第二端子;以及存取晶体管，形成在所述半导体衬底上，并且具有连接到位的第一和第二端子线路和晶闸管元件的第一端子，以及控制部分，其包括负载电流元件，其负载电流在读出操作时流向晶闸管元件的第二端子侧并被配置为对存储器执行访问控制细胞。

46. 发明申请

US20070217260A1 Semiconductor memory device and its operation method 失效
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20070217260A1
公开(公告)日：2007-09-20
申请号：US11715413
申请日：2007-03-08
申请人： Makoto Kitagawa
发明人： Makoto Kitagawa
IPC分类号： G11C16/04
CPC分类号： G11C11/405 , G11C7/12 , G11C7/18 , G11C8/16 , G11C11/4094 , G11C11/4097 , G11C2207/005 , G11C2207/2281 , G11C2207/229
摘要： A semiconductor memory device includes a memory-cell array, a read bit line, a write bit line, a sense amplifier, a first sense line, a second sense line, a first bit line switch, and a second bit line switch. The memory-cell array is laid out to form an array. The read bit line is shared by plural memory cells and connected to a data output node. The write bit line is shared by plural memory cells and connected to a data input node. The sense amplifier is configured to sense a difference in electric potential. The first sense line is connected to one of the input terminals. The second sense line is connected to the other input terminal. The first bit line switch is configured to control electrical connection and disconnection. The second bit line switch is configured to control electrical connection and disconnection.
摘要翻译：半导体存储器件包括存储单元阵列，读位线，写位线，读出放大器，第一感测线，第二感测线，第一位线开关和第二位线开关。存储单元阵列被布置成形成阵列。读位线由多个存储器单元共享并连接到数据输出节点。写位线由多个存储器单元共享并连接到数据输入节点。感测放大器被配置为感测电位差。第一感测线连接到输入端之一。第二感测线连接到另一输入端。第一位线开关配置为控制电气连接和断开。第二位线开关被配置为控制电气连接和断开。

47. 发明申请

US20060208991A1 Display 失效
标题翻译：显示
公开(公告)号：US20060208991A1
公开(公告)日：2006-09-21
申请号：US11283045
申请日：2005-11-21
申请人： Tamotsu Uekuri , Yusuke Tsutsui , Makoto Kitagawa
发明人： Tamotsu Uekuri , Yusuke Tsutsui , Makoto Kitagawa
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G3/3614 , G09G3/3677 , G09G2300/0876 , G09G2310/06
摘要： A display capable of rendering flickering hard to visually recognize, reducing power consumption and simplifying the structure of a circuit for negatively/positively reversing an image is provided. This display comprises a plurality of drain lines and a plurality of gate lines, a first pixel portion and a second pixel portion each including a subsidiary capacitor having a first electrode and a second electrode and a first subsidiary capacitance line and a second subsidiary capacitance line connected to the subsidiary capacitors of the first pixel portion and the second pixel portion respectively. The display also comprises a signal supply circuit supplying either a first signal or a second signal for negatively/positively reversing an image to the first subsidiary capacitance line of the first pixel portion when displaying the image while supplying either a third signal or a fourth signal for negatively/positively reversing the image to the second subsidiary capacitance line of the second pixel portion when reversing the image.
摘要翻译：本发明提供了一种显示器，其能够呈现出难以视觉识别的闪烁，降低功耗并简化了电路的结构，从而使/否正反转图像。该显示器包括多个漏极线和多条栅极线，第一像素部分和第二像素部分，每个包括具有第一电极和第二电极的辅助电容器和第二辅助电容线路以及连接到第二辅助电容线路的第二像素部分分别到第一像素部分和第二像素部分的辅助电容器。显示器还包括信号供给电路，当显示图像时，向第一像素部分的第一辅助电容线提供第一信号或第二信号，用于负/正反转图像，同时提供第三信号或第四信号当图像反转时，负/正反转图像到第二像素部分的第二辅助电容线。

48. 发明授权

US07091946B2 Display device 失效
标题翻译：显示设备
公开(公告)号：US07091946B2
公开(公告)日：2006-08-15
申请号：US10454777
申请日：2003-06-05
申请人： Yusuke Tsutsui , Makoto Kitagawa , Mitsugu Kobayashi
发明人： Yusuke Tsutsui , Makoto Kitagawa , Mitsugu Kobayashi
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G2310/0248 , G09G2310/04 , G09G2330/021
摘要： A mask circuit is provided in a display device having a plurality of pixels. The mask circuit supplies a video signal to each of the pixels in a partial display area selected based on a display area selection signal, and prevents the supply of the video signal to each of the pixels in a background display area. Accordingly, this display device displays an arbitrary pattern at an arbitrary position of the display panel of the display device. In addition, an inverting controlling circuit is provided for inverting the background display signal supplied to each of the pixels in the background display area for each frame. The power consumption of the display device can be reduced.
摘要翻译：在具有多个像素的显示装置中设置有掩模电路。掩模电路将视频信号提供给基于显示区域选择信号选择的部分显示区域中的每个像素，并且防止视频信号提供给背景显示区域中的每个像素。因此，该显示装置在显示装置的显示面板的任意位置显示任意图案。此外，提供反转控制电路，用于反转提供给每帧的背景显示区域中的每个像素的背景显示信号。可以减少显示装置的功耗。

49. 发明授权

US07030871B2 Active matrix display device 有权
公开(公告)号：US07030871B2
公开(公告)日：2006-04-18
申请号：US10206800
申请日：2002-07-29
申请人： Makoto Kitagawa , Mitsugu Kobayashi , Makoto Fujioka
发明人： Makoto Kitagawa , Mitsugu Kobayashi , Makoto Fujioka
IPC分类号： G09G5/00
CPC分类号： G09G3/2092 , G09G3/3648 , G09G5/12 , G09G5/39 , G09G2300/08 , G09G2320/10 , G09G2330/021 , G09G2360/18
摘要： This invention is directed to the active matrix display device with an imaging speed rapid enough for the moving image display and the small power consumption. The selector makes the switch between the moving image mode, where the image signal consecutively inputted is consecutively displayed after the certain processing is performed by the data processing unit and the still image mode, where the display is made based on the image signal stored in the frame memory. The messy display upon the switching between the modes can be prevented by differentiating the switching timing of the still to moving image mode from that of the moving to still image mode, improving the display quality.

50. 发明授权

US06891427B2 Charge pump type power supply circuit and driving circuit for display device and display device using such power supply circuit 有权
标题翻译：电荷泵型电源电路和显示装置的驱动电路以及使用这种电源电路的显示装置
公开(公告)号：US06891427B2
公开(公告)日：2005-05-10
申请号：US09823328
申请日：2001-03-29
申请人： Yusuke Tsutsui , Makoto Kitagawa , Mitsugu Kobayashi , Hisao Uehara
发明人： Yusuke Tsutsui , Makoto Kitagawa , Mitsugu Kobayashi , Hisao Uehara
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , H02M1/36 , H02M3/07 , G09G5/00
CPC分类号： H02M1/36 , G09G3/3696 , H02M3/07
摘要： A driving circuit of a display device such as a liquid crystal generates power supply clocks (1 and 2) based on a system clock during the normal display operation which is not a power save mode. The generated power supply clocks are supplied, directly or after inversion, to the switches (SW1 through SW4 (and SW5 through SW8)) in a charge pump type power supply circuit (300) for switching the connection of capacitors (C1 and C2 (and C11 and C12)) in the power supply circuit (300). In this manner, supply voltages VDD2 and VDD3 which function as the driving power supply for a driving circuit (100) and a display panel (200) can be obtained at the power supply circuit (300) by boosting the input voltage Vin. The driving circuit (100) stops supply of the power supply clocks to the power supply circuit (300) when a transition to the power save mode is instructed and a power save control signal generated by a CPU I/F circuit (16) is changed, thereby suspending generation of the supply voltage an consumption of power consumption at the circuit and display panel.
摘要翻译：诸如液晶的显示装置的驱动电路在不是省电模式的正常显示操作期间基于系统时钟产生电源时钟（1和2）。在用于切换电容器（C）的连接的电荷泵型电源电路（300）中，将所产生的电源时钟直接或反转后提供给开关（SW 1至SW 4（和SW 5至SW 8）） 1和C 2（和C 11和C 12））。以这种方式，通过升压输入电压Vin，可以在电源电路（300）获得用作驱动电路（100）和显示面板（200）的驱动电源的电源电压VDD 2和VDD 3。驱动电路（100）在指示向省电模式的转变时停止向电源电路（300）供给电源时钟，并且由CPU I / F电路（16）产生的省电控制信号发生变化从而暂停生成电源电压消耗电路和显示面板的功耗。

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