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41. 发明申请

US20070045686A1 Ferromagnetic memory cell and methods of making and using the same 有权
标题翻译：铁磁记忆单元及其制造和使用方法
公开(公告)号：US20070045686A1
公开(公告)日：2007-03-01
申请号：US11216387
申请日：2005-08-31
申请人： Kangguo Cheng , Herbert Ho , Louis Hsu , Jack Mandelman
发明人： Kangguo Cheng , Herbert Ho , Louis Hsu , Jack Mandelman
IPC分类号： H01L29/94
CPC分类号： G11C11/15 , H01L27/1203 , H01L43/065
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory cell that includes (1) a semiconductor fin enclosure formed on an insulating layer of a substrate; and (2) a ferromagnetic material within the semiconductor fin enclosure. A top surface of the ferromagnetic material is below a top surface of the semiconductor fin enclosure. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是存储单元，其包括：（1）形成在基板的绝缘层上的半导体翅片外壳; 和（2）半导体翅片外壳内的铁磁材料。铁磁材料的顶表面位于半导体翅片外壳的顶表面之下。提供了许多其他方面。

42. 发明申请

US20070040276A1 Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application 有权
标题翻译：采用埋入导电层的特征，用于电抗保险丝应用的电介质
公开(公告)号：US20070040276A1
公开(公告)日：2007-02-22
申请号：US11207218
申请日：2005-08-19
申请人： Chih-Chao Yang , Lawrence Clevenger , Timothy Dalton , Nicholas Fuller , Louis Hsu
发明人： Chih-Chao Yang , Lawrence Clevenger , Timothy Dalton , Nicholas Fuller , Louis Hsu
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/5252 , H01L21/76843 , H01L21/76844 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.
摘要翻译：提供了一种抗熔丝结构，其包括掩埋的导电的，例如作为反熔丝材料的金属层以及形成这种抗熔丝结构的方法。根据本发明，本发明的抗熔丝结构包括互连之间的漏电介质区域。当两个相邻的互连被偏置时，这些原始互连之间的电阻开始减小，并且引起时间依赖介质击穿TDDB现象。也可以通过增加局部温度来加速相邻互连之间的电阻的降低。

43. 发明申请

US20070023806A1 Method and structure for forming slot via bitline for MRAM devices 有权
标题翻译：用于通过MRAM器件的位线形成槽的方法和结构
公开(公告)号：US20070023806A1
公开(公告)日：2007-02-01
申请号：US11193660
申请日：2005-07-29
申请人： Michael Gaidis , Carl Radens , Lawrence Clevenger , Timothy Dalton , Louis Hsu , Keith Hon Wong , Chih-Chao Yang
发明人： Michael Gaidis , Carl Radens , Lawrence Clevenger , Timothy Dalton , Louis Hsu , Keith Hon Wong , Chih-Chao Yang
IPC分类号： H01L29/94
CPC分类号： B82Y10/00 , H01L27/222 , H01L43/12
摘要： A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.
摘要翻译：磁性随机存取存储器（MRAM）器件包括形成在下布线层上的磁隧道结（MTJ）堆叠，形成在MTJ堆叠上的硬掩模和形成在硬掩模上的上布线层。上布线层包括经由位于其中的位线的槽，槽经由与硬掩模接触的位线并与部分地围绕硬掩模的侧壁的蚀刻停止层接触。

44. 发明申请

US20070001736A1 Variable-gain-amplifier based limiter to remove amplitude modulation from a VCO output 失效
公开(公告)号：US20070001736A1
公开(公告)日：2007-01-04
申请号：US11155848
申请日：2005-06-17
申请人： Herschel Ainspan , Gautam Gangasani , Louis Hsu , Jack Mandelman
发明人： Herschel Ainspan , Gautam Gangasani , Louis Hsu , Jack Mandelman
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： An apparatus and method for generating high-speed clock signals using a voltage-controlled-oscillator (VCO) device. The apparatus implements a linear variable gain amplifier rather than a non-linear hard limiter to remove unwanted signal modulation in VCO output signals. Implementation of the linear variable gain amplifier leads to the generation of amplitude modulation-free oscillation leading to the generation of jitter free high frequency clock signals.

45. 发明申请

US20060234443A1 MIM capacitor and method of fabricating same 有权
标题翻译： MIM电容器及其制造方法
公开(公告)号：US20060234443A1
公开(公告)日：2006-10-19
申请号：US11106887
申请日：2005-04-15
申请人： Chih-Chao Yang , Lawrence Clevenger , Timothy Dalton , Louis Hsu
发明人： Chih-Chao Yang , Lawrence Clevenger , Timothy Dalton , Louis Hsu
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L23/5223 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A damascene MIM capacitor and a method of fabricating the MIM capacitor. The MIN capacitor includes a dielectric layer having top and bottom surfaces; a trench in the dielectric layer, the trench extending from the top surface to the bottom surface of the dielectric layer; a first plate of a MIM capacitor comprising a conformal conductive liner formed on all sidewalls and extending along a bottom of the trench, the bottom of the trench coplanar with the bottom surface of the dielectric layer; an insulating layer formed over a top surface of the conformal conductive liner; and a second plate of the MIM capacitor comprising a core conductor in direct physical contact with the insulating layer, the core conductor filling spaces in the trench not filled by the conformal conductive liner and the insulating layer. The method includes forming portions of the MIM capacitor simultaneously with damascene interconnection wires.
摘要翻译：一种镶嵌MIM电容器和一种制造MIM电容器的方法。 MIN电容器包括具有顶表面和底表面的电介质层; 电介质层中的沟槽，沟槽从电介质层的顶表面延伸到底表面; MIM电容器的第一板包括形成在所有侧壁上并沿着沟槽的底部延伸的共形导电衬垫，沟槽的底部与电介质层的底表面共面; 绝缘层，形成在所述共形导电衬垫的顶表面上; 以及MIM电容器的第二板，其包括与所述绝缘层直接物理接触的芯导体，所述芯导体填充所述沟槽中的未被所述共形导电衬垫和所述绝缘层填充的空间。该方法包括与镶嵌互连线同时形成MIM电容器的部分。

46. 发明申请

US20060220688A1 Precision tuning of a phase-change resistive element 有权
标题翻译：相变电阻元件的精密调谐
公开(公告)号：US20060220688A1
公开(公告)日：2006-10-05
申请号：US11098078
申请日：2005-04-04
申请人： Louis Hsu , Brian Ji , Chung Lam
发明人： Louis Hsu , Brian Ji , Chung Lam
IPC分类号： H03K5/22
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0064 , G11C2013/0054
摘要： The present invention comprises a method and structure for programming an on-chip phase-change resistor to a target resistance. Using an off-chip precision resistor as a reference, a state-machine determines a difference between the resistance of an on-chip resistor and the target resistance. Based upon this difference, the state machine directs a pulse generator to apply set or reset pulses to the on-chip resistor in order to decrease or increase, respectively, the resistance of the resistor, as necessary. In order to program the resistance of the phase-change resistor to a tight tolerance, it is successively reset and set by applying progressively decreasing numbers of reset pulses and set pulses, respectively, until the number of set pulses is equal to one and the target resistance of the on-chip resistor is reached.
摘要翻译：本发明包括用于将片上相变电阻器编程为目标电阻的方法和结构。使用片外精密电阻器作为参考，状态机确定片上电阻器的电阻与目标电阻之间的差。基于这种差异，状态机引导脉冲发生器将片上电阻器设置或复位脉冲施加到片上电阻器，以便根据需要分别降低或增加电阻器的电阻。为了将相变电阻器的电阻编程为严格的公差，通过分别逐渐递减的复位脉冲数和设定脉冲数来连续复位和设置，直到设定脉冲数等于1，目标值达到片上电阻的电阻。

47. 发明申请

US20060159200A1 FRONT END INTERFACE FOR DATA RECEIVER 失效
标题翻译：数据接收器的前端接口
公开(公告)号：US20060159200A1
公开(公告)日：2006-07-20
申请号：US10905705
申请日：2005-01-18
申请人： Louis Hsu , Matt Cordrey-Gale , James Mason , Phillip Murfet , Karl Selander , Michael Sorna , Huihao Xu
发明人： Louis Hsu , Matt Cordrey-Gale , James Mason , Phillip Murfet , Karl Selander , Michael Sorna , Huihao Xu
IPC分类号： H04L27/22
CPC分类号： H04L25/0274 , H04L25/0296
摘要： A data receiver is provided which includes a front end interface circuit having an alternating current (AC) transmission receiving mode and a direct current (DC) transmission receiving mode. The front end interface circuit includes an offset compensation circuit operable to compensate a DC voltage offset between a pair of differential signals input to the data receiver. The front end interface circuit further includes an AC/DC selection unit operable to switch between (a) the DC transmission receiving mode, and (b) the AC transmission receiving mode, such that the data receiver is operable in (i) the DC transmission mode in which the offset compensation circuit is disabled, (ii) the DC transmission mode in which the offset compensation circuit is enabled, (iii) the AC transmission mode in which the offset compensation circuit is disabled, and (iv) the AC transmission receiving mode in which the offset compensation circuit is enabled.
摘要翻译：提供一种数据接收器，其包括具有交流（AC）发送接收模式和直流（DC）发送接收模式的前端接口电路。前端接口电路包括偏移补偿电路，其可操作以补偿输入到数据接收器的一对差分信号之间的直流电压偏移。前端接口电路还包括可操作以在（a）直流发送接收模式和（b）交流发送接收模式之间切换的AC / DC选择单元，使得数据接收器可操作于（i）直流传输偏移补偿电路被禁用的模式，（ii）使能偏移补偿电路的直流传输模式，（iii）偏移补偿电路被禁用的AC传输模式，以及（iv）AC传输接收偏移补偿电路使能的模式。

48. 发明申请

US20060158229A1 IMPROVED SIGNAL DETECTOR FOR HIGH-SPEED SERDES 失效
标题翻译：改进的高速伺服信号检测器
公开(公告)号：US20060158229A1
公开(公告)日：2006-07-20
申请号：US10905704
申请日：2005-01-18
申请人： Louis Hsu , Karl Selander , Michael Sorna
发明人： Louis Hsu , Karl Selander , Michael Sorna
IPC分类号： H03K5/19
CPC分类号： H03K5/19 , G01R19/165
摘要： An improved signal detector system implementable in a high-speed SerDes receiver core that is able to detect valid signals from noise signals with a much tighter tolerance. The signal detector system improves upon the prior art designs by implementing modifications including: (1) the use of two peaking amplifiers for both (differential) input signals and reference to track and cancel gain variation; and, (2) the reduction of current mirroring stages to cut down current mapping error.
摘要翻译：改进的信号检测器系统可实现在高速SerDes接收机核心中，能够以更严格的公差检测来自噪声信号的有效信号。信号检测器系统通过实施修改来改进现有技术的设计，包括：（1）使用两个峰值放大器用于（差分）输入信号和参考跟踪和消除增益变化; 和（2）减少当前镜像阶段以减少当前的映射误差。

49. 发明申请

US20060110851A1 Methods for forming co-planar wafer-scale chip packages 有权
标题翻译：用于形成共面晶片级芯片封装的方法
公开(公告)号：US20060110851A1
公开(公告)日：2006-05-25
申请号：US10994494
申请日：2004-11-20
申请人： Lloyd Burrell , Howard Chen , Louis Hsu , Wolfgang Sauter
发明人： Lloyd Burrell , Howard Chen , Louis Hsu , Wolfgang Sauter
IPC分类号： H01L21/48 , H01L21/50
CPC分类号： H01L23/5389 , H01L21/52 , H01L23/147 , H01L23/5385 , H01L2221/68322 , H01L2221/68345 , H01L2924/0002 , H01L2924/1433 , H01L2924/00
摘要： Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.
摘要翻译：提出了用于形成共面多芯片晶片级封装的经济方法。部分晶片接合和部分晶片切割技术用于制造芯片以及口袋。然后将完成的芯片安装在载体基板的相应凹穴中，并且芯片之间的全局互连形成在成品芯片的顶部平坦表面上。所提出的方法促进了用不同工艺步骤和材料制造的芯片的集成。不需要使用诸如化学机械抛光剂的平面化处理来平坦化芯片的顶表面。由于芯片精确地对准并且所有芯片都朝上安装，所以模块准备好进行全局布线，从而不需要将芯片从倒置的位置翻转。

50. 发明申请

US20060109117A1 Apparatus and Method of Intelligent Multistage System Deactivation 审中-公开
标题翻译：智能多级系统停用的装置与方法
公开(公告)号：US20060109117A1
公开(公告)日：2006-05-25
申请号：US10904664
申请日：2004-11-22
申请人： Louis Hsu , Lawrence Clevenger , Carl Radens , Kwong Wong , Chih-Chao Yang , Timothy Dalton
发明人： Louis Hsu , Lawrence Clevenger , Carl Radens , Kwong Wong , Chih-Chao Yang , Timothy Dalton
IPC分类号： G08B13/14
CPC分类号： G06F21/554 , G06F21/81 , G06F21/86
摘要： A deactivation management unit for facilitating an intelligent multistage system deactivation process where the deactivation management unit is flexible, facilitates recovery, and renders reverse engineering nearly impossible after the system has been permanently deactivated.
摘要翻译：一种停用管理单元，用于促进智能多级系统停用过程，其中停用管理单元是灵活的，便于恢复，并且在系统被永久停用之后几乎不可能实现逆向工程。

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