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41. 发明授权

US06232154B1 Optimized decoupling capacitor using lithographic dummy filler 有权
标题翻译：使用光刻虚拟填料的优化去耦电容器
公开(公告)号：US06232154B1
公开(公告)日：2001-05-15
申请号：US09442890
申请日：1999-11-18
申请人： Armin M. Reith , Louis Hsu , Henning Haffner , Gunther Lehmann
发明人： Armin M. Reith , Louis Hsu , Henning Haffner , Gunther Lehmann
IPC分类号： H01L2182
CPC分类号： H01L28/40 , H01L27/10861 , H01L27/10894 , H01L27/10897
摘要： A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.
摘要翻译：使用现有的平版印刷填料，优化大型集成电路（VLSI）的去耦电容的尺寸和填充的方法。该方法将自动或手动生成光刻填充图案与电容器的形成相结合。根据该方法，当芯片布局即将完成时，芯片上剩余的空余空间由布局工具识别。然后，最近的电源网络被提取。所有电源及其组合在连接表中排序，一旦电源网最接近从布局提取的空白空间中，则确定适当类型的电容。然后空的空间被分配适当的去耦电容。通过该方法产生的去耦电容适用于降低噪声的VLSI电源。

42. 发明授权

US07657995B2 Method of fabricating a microelectromechanical system (MEMS) switch 失效
标题翻译：制造微机电系统（MEMS）开关的方法
公开(公告)号：US07657995B2
公开(公告)日：2010-02-09
申请号：US11776835
申请日：2007-07-12
申请人： Louis Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
发明人： Louis Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01H11/00 , H01H65/00
CPC分类号： H01H59/0009 , H01H1/20 , H01H2001/0084 , H01H2001/0089 , Y10T29/49105 , Y10T29/49128 , Y10T29/49155 , Y10T29/49204 , Y10T29/49208
摘要： A method of fabricating a MEMS switch that is fully integratable in a semiconductor fabrication line. The method consists of forming two posts, each end thereof terminating in a cap; a rigid movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; forming upper and lower electrode pairs and upper and lower interconnect wiring lines connected and disconnected by the rigid movable conductive plate. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines.
摘要翻译：一种制造可在半导体制造生产线中完全集成的MEMS开关的方法。该方法包括形成两个柱，其每端终止于盖中; 刚性可移动导电板，其表面终止于两个相对边缘中的每一个中的环中，所述环松散地连接到引导柱; 形成上下电极对以及由刚性可移动导电板连接和断开的上下互连布线。导电板向上移动，使两条上部互连线路短路。相反，当电压施加到下电极对时，导电板向下移动，而上电极对接地，使两个下互连布线短路并打开上布线。

43. 发明申请

US20090312046A1 INTELLIGENT WIRELESS POWER CHARGING SYSTEM 有权
标题翻译：智能无线充电系统
公开(公告)号：US20090312046A1
公开(公告)日：2009-12-17
申请号：US12137185
申请日：2008-06-11
申请人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens
发明人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens
IPC分类号： H04B7/00 , H04M1/00
CPC分类号： H02J50/20 , H02J7/025 , H02J17/00
摘要： A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging.
摘要翻译：一种用于无线网络设备智能电源管理的系统和方法。该系统通过无线电力充电方法提供可靠的无线通信，以及在无线设备中维持电池的电力容量的方法。电池通过嵌入在无线设备内部的射频收集单元进行充电。智能无线电力充电系统还包括耦合到AC电力线的至少两个电池和至少两个RF适配器装置。第一个适配器设置为数据通信，而第二个适配器用于传输电源。此外，当在活动模式期间使用第一电池时，对第二电池进行无线充电。

44. 发明授权

US07545161B2 Method and apparatus to measure threshold shifting of a MOSFET device and voltage difference between nodes 失效
标题翻译：测量MOSFET器件的阈值偏移和节点之间的电压差的方法和装置
公开(公告)号：US07545161B2
公开(公告)日：2009-06-09
申请号：US11832796
申请日：2007-08-02
申请人： Louis Hsu , Jong-Ru Guo , Ping-Chuan Wang , Zhijian Yang
发明人： Louis Hsu , Jong-Ru Guo , Ping-Chuan Wang , Zhijian Yang
IPC分类号： G01R31/02
CPC分类号： G01R31/2621
摘要： An on-chip circuit to quantitatively measure threshold voltage shifts of a MOSFET. The circuit includes a programmable Vt reference sensor; a programmable Vt monitoring sensor; and a comparator for receiving inputs from the reference and monitoring sensors providing an output flag signal. The shifting of the MOSFET device voltage threshold monitors process variations, geometry sensitivity, plasma damage, stress, and hot carriers and other device damages. The same circuit also measures voltage differences between any two nodes in an integrated circuit chip or wafer.
摘要翻译：用于定量测量MOSFET的阈值电压偏移的片上电路。该电路包括可编程Vt参考传感器; 可编程Vt监控传感器; 以及比较器，用于从提供输出标志信号的参考和监视传感器接收输入。 MOSFET器件电压阈值的偏移可以监视工艺变化，几何感应，等离子体损伤，应力和热载体以及其他器件损坏。相同的电路还测量集成电路芯片或晶片中的任何两个节点之间的电压差。

45. 发明申请

US20080079172A1 METHOD FOR FABRICATING AND BEOL INTERCONNECT STRUCTURES WITH SIMULTANEOUS FORMATION OF HIGH-K AND LOW-K DIELECTRIC REGIONS 有权
标题翻译：同时形成高K和低K介电区域的制造和波形互连结构的方法
公开(公告)号：US20080079172A1
公开(公告)日：2008-04-03
申请号：US11939671
申请日：2007-11-14
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L23/52
CPC分类号： H01L23/5329 , H01L21/7682 , H01L21/76849 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： A method for fabricating and back-end-of-line (BEOL) metalization structures includes simultaneous high-k and low-k dielectric regions. An interconnect structure includes a first inter-level dielectric (ILD) layer and a second ILD layer with the first ILD layer underlying the second ILD layer. A plurality of columnar air gaps is formed in the first ILD. The columnar air gap structure is created using a two-phase photoresist material for providing different etching selectivity during subsequent processing.
摘要翻译：一种用于制造和后端（BEOL）金属化结构的方法包括同时存在的高k和低k电介质区域。互连结构包括第一层间电介质（ILD）层和具有位于第二ILD层下面的第一ILD层的第二ILD层。在第一ILD中形成多个柱状气隙。使用两相光致抗蚀剂材料制造柱状气隙结构，用于在随后的处理期间提供不同的蚀刻选择性。

46. 发明申请

US20080067608A1 Storage Elements with Disguised Configurations and Methods of Using the Same 审中-公开
标题翻译：具有伪装配置的存储元件及其使用方法
公开(公告)号：US20080067608A1
公开(公告)日：2008-03-20
申请号：US11928663
申请日：2007-10-30
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L27/06
CPC分类号： H01L23/585 , H01L23/5256 , H01L27/101 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In a first aspect, a first apparatus is provided. The first apparatus is an element of an integrated circuit (IC) having (1) a metal-oxide-semiconductor field-effect transistor (MOSFET) having source/drain diffusion regions; (2) an electrical fuse (eFuse) coupled to the MOSFET such that a portion of the eFuse serves as a gate region of the MOSFET; and (3) an implanted region coupled to the source/drain diffusion regions of the MOSFET such that a path between the source/drain diffusion regions functions as a short circuit or an open circuit. In another aspect, a design structure embodied in a machine readable medium for designing manufacturing, or testing a design is provided. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是具有（1）具有源极/漏极扩散区域的金属氧化物半导体场效应晶体管（MOSFET）的集成电路（IC）的元件; （2）耦合到所述MOSFET的电熔丝（eFuse），使得所述eFuse的一部分用作所述MOSFET的栅极区域; 和（3）耦合到MOSFET的源极/漏极扩散区域的注入区域，使得源极/漏极扩散区域之间的路径用作短路或开路。在另一方面，提供了体现在用于设计制造的机器可读介质或测试设计中的设计结构。提供了许多其他方面。

47. 发明申请

US20080054349A1 REDUCED-RESISTANCE FINFETS BY SIDEWALL SILICIDATION AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：通过小型硅胶制造的耐磨损金属及其制造方法
公开(公告)号：US20080054349A1
公开(公告)日：2008-03-06
申请号：US11933392
申请日：2007-10-31
申请人： Kangguo Cheng , Louis Hsu , Jack Mandelman , Haining Yang
发明人： Kangguo Cheng , Louis Hsu , Jack Mandelman , Haining Yang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L21/823418 , H01L21/823437 , H01L29/41791 , H01L29/665 , H01L29/6653 , H01L29/66795 , H01L29/78618 , H01L2029/7858 , Y10S438/96
摘要： In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了制造finFET的第一种方法。第一种方法包括以下步骤：（1）提供衬底; 和（2）在所述衬底上形成所述finFET的至少一个源极/漏极扩散区域。每个源极/漏极扩散区域包括（a）非硅化硅的内部区域; 和（b）硅化物形成在非硅化硅区域的顶表面和侧壁上。提供了许多其他方面。

48. 发明申请

US20080048268A1 SEMICONDUCTOR FINFET STRUCTURES WITH ENCAPSULATED GATE ELECTRODES AND METHODS FOR FORMING SUCH SEMICONDUCTOR FINFET STRUCTURES 有权
标题翻译：具有封装栅极电极的半导体FINFET结构及其形成这种半导体FINFET结构的方法
公开(公告)号：US20080048268A1
公开(公告)日：2008-02-28
申请号：US11923717
申请日：2007-10-25
申请人： Louis Hsu , Jack Mandelman
发明人： Louis Hsu , Jack Mandelman
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/66795
摘要： Semiconductor structures in which the gate electrode of a FinFET is masked from the process introducing dopant into the fin body of the FinFET to form source/drain regions and methods of fabricating such semiconductor structures. The gate doping, and hence the work function of the gate electrode, is advantageously isolated from the process that dopes the fin body to form the source/drain regions. The sidewalls of the gate electrode are covered by sidewall spacers that are formed on the gate electrode but not on the sidewall of the fin body.
摘要翻译：其中FinFET的栅极被从引入掺杂剂的工艺掩模到FinFET的鳍状体中以形成源极/漏极区域的半导体结构以及制造这种半导体结构的方法。栅极掺杂以及因此栅电极的功函数有利地与掺杂鳍体以形成源极/漏极区的过程隔离。栅电极的侧壁由形成在栅电极上但不在鳍体的侧壁上的侧壁间隔物覆盖。

49. 发明申请

US20080044959A1 BODY-CONTACTED SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATING SUCH BODY-CONTACTED SEMICONDUCTOR STRUCTURES 失效
标题翻译：人体接触半导体结构和制造这种接触式半导体结构的方法
公开(公告)号：US20080044959A1
公开(公告)日：2008-02-21
申请号：US11925352
申请日：2007-10-26
申请人： Kangguo Cheng , Louis Hsu , Jack Mandelman
发明人： Kangguo Cheng , Louis Hsu , Jack Mandelman
IPC分类号： H01L21/86
CPC分类号： H01L21/84 , H01L27/0218 , H01L27/10841 , H01L27/1203 , H01L29/66545
摘要： A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact in the buried dielectric layer of the SOI wafer. The body contact electrically couples a semiconductor body with a channel region of the access device of one vertical memory cell and a semiconductor substrate of the SOI wafer. The body contact provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by an ion implantation process that modifies the stoichiometry of a region of the buried dielectric layer so that the modified region becomes electrically conductive with a relatively high resistance.
摘要翻译：一种用于动态随机存取存储器（DRAM）单元阵列的半导体结构，其包括建立在绝缘体上半导体（SOI）晶片上的多个垂直存储单元和SOI晶片的埋入介质层中的体接触。体接触将半导体本体与一个垂直存储单元的存取器件的沟道区和SOI晶片的半导体衬底电耦合。身体接触提供了一种电流泄漏路径，可减少浮体对垂直记忆体的影响。体接触可以通过离子注入工艺形成，该方法改变掩埋介电层的区域的化学计量，使得改性区域以相对较高的电阻变为导电性。

50. 发明申请

US20070278619A1 Semiconductor integrated circuit devices having high-Q wafer back-side capacitors 有权
标题翻译：具有高Q晶片背面电容器的半导体集成电路器件
公开(公告)号：US20070278619A1
公开(公告)日：2007-12-06
申请号：US11443394
申请日：2006-05-30
申请人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L29/00
CPC分类号： H01L21/84 , H01L21/76898 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.
摘要翻译：提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

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