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41. 发明授权

US07871869B2 Extremely-thin silicon-on-insulator transistor with raised source/drain 有权
标题翻译：极薄的绝缘体上硅晶体管，具有升高的源极/漏极
公开(公告)号：US07871869B2
公开(公告)日：2011-01-18
申请号：US12543679
申请日：2009-08-19
申请人： Eduard A. Cartier , Steven J. Koester , Kingsuk Maitra , Amlan Majumdar , Renee T. Mo
发明人： Eduard A. Cartier , Steven J. Koester , Kingsuk Maitra , Amlan Majumdar , Renee T. Mo
IPC分类号： H01L21/00
CPC分类号： H01L29/6659 , H01L21/28079 , H01L29/4958 , H01L29/665 , H01L29/6653 , H01L29/66537 , H01L29/6656 , H01L29/66628 , H01L29/66772 , H01L29/78696
摘要： An extremely-thin silicon-on-insulator transistor is provided that includes a buried oxide layer above a substrate, a silicon layer above the buried oxide layer, a gate stack on the silicon layer, a nitride liner on the silicon layer and adjacent to the gate stack, an oxide liner on and adjacent to the nitride liner, and raised source/drain regions. The gate stack includes a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. Each of the raised source/drain regions has a first part comprising a portion of the silicon layer, a second part adjacent to parts of the oxide liner and the nitride liner, and a third part above the second part. Also provided is a method for fabricating an extremely-thin silicon-on-insulator transistor.
摘要翻译：提供了一种极薄的绝缘体上硅晶体管，其包括衬底上的掩埋氧化物层，掩埋氧化物层上方的硅层，硅层上的栅极堆叠，硅层上的氮化物衬垫，栅堆叠，氮化物衬垫上并与其相邻的氧化物衬垫，以及升高的源/漏区。栅极堆叠包括在硅层上的高k氧化物层和在高k氧化物层上的金属栅极。凸起的源极/漏极区域中的每一个具有包括硅层的一部分的第一部分，与氧化物衬垫和氮化物衬垫的部分相邻的第二部分，以及在第二部分上方的第三部分。还提供了制造极薄的绝缘体上硅晶体管的方法。

42. 发明申请

US20090311836A1 EXTREMELY-THIN SILICON-ON-INSULATOR TRANSISTOR WITH RAISED SOURCE/DRAIN 有权
公开(公告)号：US20090311836A1
公开(公告)日：2009-12-17
申请号：US12543679
申请日：2009-08-19
申请人： EDUARD A. CARTIER , Steven J. Koester , Kingsuk Maitra , Arnlan Majumdar , Renee T. Mo
发明人： EDUARD A. CARTIER , Steven J. Koester , Kingsuk Maitra , Arnlan Majumdar , Renee T. Mo
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/28079 , H01L29/4958 , H01L29/665 , H01L29/6653 , H01L29/66537 , H01L29/6656 , H01L29/66628 , H01L29/66772 , H01L29/78696
摘要： An extremely-thin silicon-on-insulator transistor is provided that includes a buried oxide layer above a substrate, a silicon layer above the buried oxide layer, a gate stack on the silicon layer, a nitride liner on the silicon layer and adjacent to the gate stack, an oxide liner on and adjacent to the nitride liner, and raised source/drain regions. The gate stack includes a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. Each of the raised source/drain regions has a first part comprising a portion of the silicon layer, a second part adjacent to parts of the oxide liner and the nitride liner, and a third part above the second part. Also provided is a method for fabricating an extremely-thin silicon-on-insulator transistor.

43. 发明申请

US20090243031A1 STRUCTURE AND METHOD TO CONTROL OXIDATION IN HIGH-K GATE STRUCTURES 有权
标题翻译：控制高K门结构氧化的结构和方法
公开(公告)号：US20090243031A1
公开(公告)日：2009-10-01
申请号：US12055682
申请日：2008-03-26
申请人： Wesley C. Natzle , Renee T. Mo , Rashmi Jha , Kathryn T. Schonenberg , Richard A. Conti
发明人： Wesley C. Natzle , Renee T. Mo , Rashmi Jha , Kathryn T. Schonenberg , Richard A. Conti
IPC分类号： H01L29/49 , H01L21/441
CPC分类号： H01L21/76224 , H01L21/28123 , H01L29/517
摘要： In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.
摘要翻译：在一个实施例中，本发明提供一种制造半导体器件的方法，其包括提供包括至少一个半导体区域和至少一个氧源区域的衬底; 在所述至少一个氧区的上表面的部分顶部形成氧阻隔材料; 在包括所述至少一个半导体区域的衬底上形成高k栅极电介质，其中氧阻挡材料将所述高k栅极电介质与所述至少一个氧源材料分离; 并在高k栅极电介质的顶部形成栅极导体。

44. 发明授权

US07518145B2 Integrated multiple gate dielectric composition and thickness semiconductor chip and method of manufacturing the same 失效
标题翻译：集成多栅极电介质组成和厚度半导体芯片及其制造方法
公开(公告)号：US07518145B2
公开(公告)日：2009-04-14
申请号：US11627001
申请日：2007-01-25
申请人： Anthony I. Chou , Renee T. Mo , Shreesh Narasimha
发明人： Anthony I. Chou , Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L29/10
CPC分类号： H01L21/28202 , H01L21/823462 , H01L21/823857 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A method comprises forming a material over a substrate and patterning the material to remove portions of the material and expose an underlying portion of the substrate. The method further includes performing an oxidation process to form an oxide layer over the exposed portion of the substrate and at an interface between the material and the substrate. A circuit comprises a non-critical device and an oxide formed as part of this non-critical device. A high-K dielectric material is formed over a substrate as part of the critical device within the circuit. An oxide based interface is provided between the high-K dielectric material and an underlying substrate. A second method forms a nitride or oxynitride as the first material.
摘要翻译：一种方法包括在衬底上形成材料并图案化材料以去除材料的部分并暴露衬底的下面部分。该方法还包括进行氧化处理以在衬底的暴露部分和材料与衬底之间的界面处形成氧化物层。电路包括非关键器件和形成为该非关键器件的一部分的氧化物。高K电介质材料形成在衬底上，作为电路内关键器件的一部分。在高K电介质材料和下层衬底之间提供氧化物基界面。第二种方法形成氮化物或氧氮化物作为第一种材料。

45. 发明申请

US20080179714A1 INTEGRATED MULTIPLE GATE DIELECTRIC COMPOSITION AND THICKNESS SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：集成多栅型电介质组合物和厚度半导体芯片及其制造方法
公开(公告)号：US20080179714A1
公开(公告)日：2008-07-31
申请号：US11627001
申请日：2007-01-25
申请人： Anthony I. Chou , Renee T. Mo , Shreesh Narasimha
发明人： Anthony I. Chou , Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L23/58 , H01L21/31
CPC分类号： H01L21/28202 , H01L21/823462 , H01L21/823857 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A method comprises forming a material over a substrate and patterning the material to remove portions of the material and expose an underlying portion of the substrate. The method further includes performing an oxidation process to form an oxide layer over the exposed portion of the substrate and at an interface between the material and the substrate. A circuit comprises a non-critical device and an oxide formed as part of this non-critical device. A high-K dielectric material is formed over a substrate as part of the critical device within the circuit. An oxide based interface is provided between the high-K dielectric material and an underlying substrate. A second method forms a nitride or oxynitride as the first material.
摘要翻译：一种方法包括在衬底上形成材料并图案化材料以去除材料的部分并暴露衬底的下面部分。该方法还包括进行氧化处理以在衬底的暴露部分和材料与衬底之间的界面处形成氧化物层。电路包括非关键器件和形成为该非关键器件的一部分的氧化物。高K电介质材料形成在衬底上，作为电路内关键器件的一部分。在高K电介质材料和下层衬底之间提供氧化物基界面。第二种方法形成氮化物或氧氮化物作为第一种材料。

46. 发明授权

US07358130B2 Method for monitoring lateral encroachment of spacer process on a CD SEM 失效
标题翻译：在CD扫描电子显微镜上监测间隔物过程横向侵入的方法
公开(公告)号：US07358130B2
公开(公告)日：2008-04-15
申请号：US11482419
申请日：2006-07-07
申请人： Bachir Dirahoui , Renee T. Mo , Ravikumar Ramachandran , Eric P. Solecky
发明人： Bachir Dirahoui , Renee T. Mo , Ravikumar Ramachandran , Eric P. Solecky
IPC分类号： H01L21/8238
CPC分类号： H01L22/12
摘要： A process implementing steps for determining encroachment of a spacer structure in a semiconductor device having thick and thin spacer regions, including a transition region formed therebetween. The method steps comprise: obtaining a line width roughness (LWR) measurement at at least one location along each thick, thin and transition spacer regions; determining a threshold LWR measurement value based on the LWR measurements; defining a region of interest (ROI) and obtaining a further LWR measurement in the ROI; comparing the LWR measurement in the ROI against the threshold LWR measurement value; and, notifying a user that either encroachment of the spacer structure is present when the LWR measurement in the ROI is below the threshold LWR measurement value, or that no encroachment of the spacer structure is present when the LWR measurement in the ROI is above the threshold LWR measurement value.
摘要翻译：一种实现用于确定具有厚而薄的间隔区域的半导体器件中间隔结构的侵入的步骤的方法，包括在它们之间形成的过渡区域。方法步骤包括：在沿着每个厚的，薄的和过渡间隔区的至少一个位置处获得线宽粗糙度（LWR）测量; 基于LWR测量确定阈值LWR测量值; 定义感兴趣区域（ROI）并在ROI中获得进一步的LWR测量; 将ROI中的LWR测量值与阈值LWR测量值进行比较; 并且当ROI中的LWR测量低于阈值LWR测量值时或者当ROI中的LWR测量高于阈值时不通知间隔物结构的侵入，通知用户是否存在间隔结构的侵入 LWR测量值。

47. 发明申请

US20120187400A1 TEST STRUCTURE FOR DETECTION OF GAP IN CONDUCTIVE LAYER OF MULTILAYER GATE STACK 有权
标题翻译：用于检测多层栅格导体层中GAP的测试结构
公开(公告)号：US20120187400A1
公开(公告)日：2012-07-26
申请号：US13013133
申请日：2011-01-25
申请人： Renee T. Mo , Oliver D. Patterson , Xing Zhou
发明人： Renee T. Mo , Oliver D. Patterson , Xing Zhou
IPC分类号： H01L21/66 , H01L23/528
CPC分类号： H01L29/49 , H01L22/34
摘要： A semiconductor structure including a test structure for detection of a gap in a conductive layer of the semiconductor structure includes a semiconductor substrate; the test structure, the test structure being located on the semiconductor substrate, the test structure comprising a multilayer gate stack, wherein the multilayer gate stack includes a single conductive layer region including: a gate dielectric located on the semiconductor substrate; the conductive layer located on the gate dielectric; and an undoped amorphous silicon layer located on the conductive layer; and wherein the test structure is configured to detect the presence of the gap in the conductive layer.
摘要翻译：包括用于检测半导体结构的导电层中的间隙的测试结构的半导体结构包括半导体衬底; 所述测试结构位于所述半导体衬底上，所述测试结构包括多层栅极叠层，其中所述多层栅极叠层包括单个导电层区域，所述单个导电层区域包括位于所述半导体衬底上的栅极电介质; 位于栅极电介质上的导电层; 以及位于所述导电层上的未掺杂非晶硅层; 并且其中所述测试结构被配置为检测所述导电层中的间隙的存在。

48. 发明授权

US08101518B2 Method and process for forming a self-aligned silicide contact 有权
标题翻译：用于形成自对准硅化物接触的方法和工艺
公开(公告)号：US08101518B2
公开(公告)日：2012-01-24
申请号：US12136885
申请日：2008-06-11
申请人： Cyril Cabral, Jr. , Michael A. Cobb , Asa Frye , Balasubramanian S. Pranatharthi Haran , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Andrew P. Mansson , Renee T. Mo , Jay W. Strane , Horatio S. Wildman
发明人： Cyril Cabral, Jr. , Michael A. Cobb , Asa Frye , Balasubramanian S. Pranatharthi Haran , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Andrew P. Mansson , Renee T. Mo , Jay W. Strane , Horatio S. Wildman
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665
摘要： The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step A. selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.
摘要翻译：本发明提供一种形成自对准Ni合金硅化物接触的方法。本发明的方法首先首先用Pt和任选的以下金属Pd，Rh，Ti，V，Cr，Zr，Nb，Mo，Hf，Ta，W或Re中的至少一种沉积导电Ni合金，整个半导体结构，其包括至少一个栅极堆叠区域。包含例如Ti，TiN或W的氧扩散阻挡层沉积在结构上以防止金属的氧化。然后使用退火步骤在金属与硅接触的区域中形成NiSi，PtSi接触。在退火步骤A期间，与绝缘材料（例如SiO 2和Si 3 N 4）直接接触的金属不会转化为金属合金硅化物接触。然后进行选择性蚀刻步骤以从间隔物和沟槽隔离区域的侧壁去除未反应的金属。

49. 发明授权

US08039382B2 Method for forming self-aligned metal silicide contacts 有权
标题翻译：用于形成自对准金属硅化物接触的方法
公开(公告)号：US08039382B2
公开(公告)日：2011-10-18
申请号：US12539660
申请日：2009-08-12
申请人： Sunfei Fang , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Renee T. Mo , Balasubramanian Pranatharthiharan , Jay W. Strane
发明人： Sunfei Fang , Randolph F. Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Renee T. Mo , Balasubramanian Pranatharthiharan , Jay W. Strane
IPC分类号： H01L21/00
CPC分类号： H01L21/28518 , C23F1/28 , C23F1/30 , C23F1/44
摘要： The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.
摘要翻译：本发明涉及一种用于在由暴露的电介质区彼此间隔开的至少两个含硅半导体区域上形成自对准金属硅化物接触的方法。优选地，如此形成的每个自对准金属硅化物触点至少包括具有基本平滑表面的至少硅化镍和铂硅化物，并且暴露的电介质区域基本上不含金属和金属硅化物。更优选地，该方法包括镍或镍合金沉积，低温退火，镍蚀刻，高温退火和王水腐蚀的步骤。

50. 发明授权

US07781321B2 Electroless metal deposition for dual work function 失效
标题翻译：无功金属沉积双功能功能
公开(公告)号：US07781321B2
公开(公告)日：2010-08-24
申请号：US12117769
申请日：2008-05-09
申请人： Jeffrey P. Gambino , Michael P. Chudzik , Renee T. Mo
发明人： Jeffrey P. Gambino , Michael P. Chudzik , Renee T. Mo
IPC分类号： H01L21/44
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/82345 , H01L21/823462 , H01L29/4966 , H01L29/517
摘要： The present invention, in one embodiment provides a method of forming a semiconducting device including providing a substrate including a semiconducting surface, the substrate comprising a first device region and a second device region; forming a high-k dielectric layer atop the semiconducting surface of the substrate; forming a block mask atop the second device region of the substrate, wherein the first device region of the substrate is exposed; forming a first metal layer atop the high-k dielectric layer present in the first device region of the substrate; removing the block mask to expose a portion of the high-k dielectric layer in the first device region of the substrate; forming a second metal layer atop the portion of the high-k dielectric layer in the second device region and atop the first metal in the first device region of the substrate; and forming gate structures in the first and second device regions of the substrate.
摘要翻译：本发明在一个实施例中提供了一种形成半导体器件的方法，包括提供包括半导体表面的衬底，该衬底包括第一器件区域和第二器件区域; 在衬底的半导体表面上方形成高k电介质层; 在所述衬底的所述第二器件区域的顶部形成掩模掩模，其中所述衬底的所述第一器件区域被暴露; 在存在于所述衬底的第一器件区域中的高k电介质层的顶部形成第一金属层; 去除所述块掩模以暴露所述衬底的所述第一器件区域中的所述高k电介质层的一部分; 在所述第二器件区域中的所述高k电介质层的所述部分的顶部形成第二金属层，并且在所述衬底的所述第一器件区域中的所述第一金属的顶部上形成第二金属层; 以及在所述衬底的所述第一和第二器件区域中形成栅极结构。

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