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41. 发明授权

US5342807A Soft bond for semiconductor dies 失效
标题翻译：半导体芯片的软键
公开(公告)号：US5342807A
公开(公告)日：1994-08-30
申请号：US976093
申请日：1992-11-13
申请人： Larry D. Kinsman , Derek J. Gochnour , Alan G. Wood , Warren M. Farnworth
发明人： Larry D. Kinsman , Derek J. Gochnour , Alan G. Wood , Warren M. Farnworth
IPC分类号： G01R1/04 , G01R1/073 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/13 , H01L23/498 , H05K3/00 , H05K3/40 , H05K3/42
CPC分类号： G01R1/0466 , G01R1/0483 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/85 , H05K3/4007 , G01R1/0735 , G01R3/00 , G01R31/2863 , H01L2224/05554 , H01L2224/16145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45124 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48455 , H01L2224/48472 , H01L2224/49171 , H01L2224/73265 , H01L2224/78313 , H01L2224/85001 , H01L2224/85099 , H01L2224/85203 , H01L2224/85205 , H01L2224/85207 , H01L2224/85214 , H01L2225/06562 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H01L2924/15151 , H01L2924/15153 , H01L2924/15165 , H01L2924/15174 , H01L2924/16195 , H01L2924/20751 , H01L2924/20753 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423 , Y10S228/904 , Y10T29/49004
摘要： On a semiconductor integrated circuit die, a semipermanent electrical connection is effected by the use of wirebond techniques, in which the parameters of the wirebond are controlled, so that less bonding force retains the leadwires to the bondpads than the attachment strength of the bondpads to the die. The wirebond techniques include attaching leadwires to bondpads on the die, using ultrasonic wedge bonding. The strength of the bond between the leadwires is significantly less than the attachment strength of the bondpads, preferably by a ratio which ensures that the bondpads are not lifted from the die when the leadwires are removed by breaking the bond between the leadwires and the bondpads. Subsequent to testing and burnin, the bond between the leadwires and the bondpads is severed. The die are then removed from the package body and the bondpads may then be attached by conventional means. The technique is useful in providing known good die.
摘要翻译：在半导体集成电路管芯上，通过使用引线接合技术来实现半永久性电连接，其中引线键合的参数被控制，使得较少的结合力将导线保持在粘合垫上，而不是粘合垫的附着强度死。引线接合技术包括使用超声波楔形接合将引线连接到管芯上的焊盘。引线之间的结合强度显着小于粘合垫的附着强度，优选地通过确保当引线通过断开引线和粘合垫之间的键而去除引线时，粘合垫不会从模具上提起的比例。在测试和燃烧之后，引线和焊盘之间的接合被切断。然后将模具从包装体中取出，然后可以通过常规方法将粘合垫连接起来。该技术在提供已知的好的模具中是有用的。

42. 发明授权

US5336649A Removable adhesives for attachment of semiconductor dies 失效
标题翻译：用于连接半导体管芯的可移除粘合剂
公开(公告)号：US5336649A
公开(公告)日：1994-08-09
申请号：US976221
申请日：1992-11-13
申请人： Larry D. Kinsman , Derek J. Gochnour , Alan G. Wood , Warren M. Farnworth
发明人： Larry D. Kinsman , Derek J. Gochnour , Alan G. Wood , Warren M. Farnworth
IPC分类号： G01R1/04 , G01R1/073 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/13 , H01L23/498 , H05K3/00 , H05K3/40 , H05K3/42
CPC分类号： G01R1/0466 , G01R1/0483 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/85 , H05K3/4007 , G01R1/0735 , G01R3/00 , G01R31/2863 , H01L2224/05554 , H01L2224/16145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45124 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48455 , H01L2224/48472 , H01L2224/49171 , H01L2224/73265 , H01L2224/78313 , H01L2224/85001 , H01L2224/85099 , H01L2224/85203 , H01L2224/85205 , H01L2224/85207 , H01L2224/85214 , H01L2225/06562 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H01L2924/15151 , H01L2924/15153 , H01L2924/15165 , H01L2924/15174 , H01L2924/16195 , H01L2924/20751 , H01L2924/20753 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423
摘要： In order to provide pretested bare semiconductor integrated circuit die, a temporary mechanical connection is effected by the use of a soluble material. A semipermanent electrical connection is effected, in which the parameters of the connection are controlled, so that the die remains functional subsequent to burnin and test. Subsequent to testing and burnin, the die are removed from the package body. The technique is useful in providing known good die.
摘要翻译：为了提供预先测试的裸半导体集成电路管芯，通过使用可溶性材料实现临时机械连接。进行半永久电连接，其中连接的参数被控制，使得模具在燃烧和测试之后保持功能。在测试和燃烧之后，将模具从包装体中取出。该技术在提供已知的好的模具中是有用的。

43. 发明授权

US08981511B2 Multi-chip package for imaging systems 有权
标题翻译：用于成像系统的多芯片封装
公开(公告)号：US08981511B2
公开(公告)日：2015-03-17
申请号：US13556009
申请日：2012-07-23
申请人： Larry D. Kinsman , Chi-Yao Kuo
发明人： Larry D. Kinsman , Chi-Yao Kuo
IPC分类号： H01L31/0232 , H01L27/146
CPC分类号： H01L27/14618 , H01L2224/32145 , H01L2224/48091 , H01L2224/73265 , H01L2924/10253 , H01L2924/00014 , H01L2924/00
摘要： A multi-chip package may include an image sensor chip, an image signal processor (ISP) chip, a cover glass, and a package substrate. The ISP chip may be placed on the substrate. The image sensor chip may be placed over the ISP chip. An adhesive film may be formed between the ISP and image sensor chips. A cover glass may be suspended above the image sensor chip. The ISP chip and the image sensor chip may be wire bonded to the substrate. The multi-chip package may be hermetically sealed using a liquid compound or a dam structure. During normal operation, the ISP chip sends control signals to the image sensor chip via a first set of wire bond members and conductive traces in the substrate while the image sensor chip sends output signals to the ISP chip via a second set of wire bond terminals and conductive traces in the substrate.
摘要翻译：多芯片封装可以包括图像传感器芯片，图像信号处理器（ISP）芯片，盖玻片和封装基板。 ISP芯片可以放置在基板上。图像传感器芯片可以放置在ISP芯片上。可以在ISP和图像传感器芯片之间形成粘合膜。盖玻片可以悬挂在图像传感器芯片上方。 ISP芯片和图像传感器芯片可以被引线接合到基板。多芯片封装可以使用液体化合物或坝结构气密密封。在正常操作期间，ISP芯片通过第一组引线键合元件和衬底中的导电迹线向图像传感器芯片发送控制信号，同时图像传感器芯片通过第二组线接端子向ISP芯片发送输出信号，衬底中的导电迹线。

44. 发明申请

US20130221470A1 MULTI-CHIP PACKAGE FOR IMAGING SYSTEMS 有权
标题翻译：成像系统的多芯片包装
公开(公告)号：US20130221470A1
公开(公告)日：2013-08-29
申请号：US13556009
申请日：2012-07-23
申请人： Larry D. Kinsman , Chi-Yao Kuo
发明人： Larry D. Kinsman , Chi-Yao Kuo
IPC分类号： H01L31/0203 , H01L25/16 , H01L31/18
CPC分类号： H01L27/14618 , H01L2224/32145 , H01L2224/48091 , H01L2224/73265 , H01L2924/10253 , H01L2924/00014 , H01L2924/00
摘要： A multi-chip package may include an image sensor chip, an image signal processor (ISP) chip, a cover glass, and a package substrate. The ISP chip may be placed on the substrate. The image sensor chip may be placed over the ISP chip. An adhesive film may be formed between the ISP and image sensor chips. A cover glass may be suspended above the image sensor chip. The ISP chip and the image sensor chip may be wire bonded to the substrate. The multi-chip package may be hermetically sealed using a liquid compound or a dam structure. During normal operation, the ISP chip sends control signals to the image sensor chip via a first set of wire bond members and conductive traces in the substrate while the image sensor chip sends output signals to the ISP chip via a second set of wire bond terminals and conductive traces in the substrate.
摘要翻译：多芯片封装可以包括图像传感器芯片，图像信号处理器（ISP）芯片，盖玻片和封装基板。 ISP芯片可以放置在基板上。图像传感器芯片可以放置在ISP芯片上。可以在ISP和图像传感器芯片之间形成粘合膜。盖玻片可以悬挂在图像传感器芯片上方。 ISP芯片和图像传感器芯片可以被引线接合到基板。多芯片封装可以使用液体化合物或坝结构气密密封。在正常操作期间，ISP芯片通过第一组引线键合元件和衬底中的导电迹线向图像传感器芯片发送控制信号，同时图像传感器芯片通过第二组线接端子向ISP芯片发送输出信号，衬底中的导电迹线。

45. 发明授权

US07227261B2 Vertical surface mount assembly and methods 有权
标题翻译：垂直表面安装组件及方法
公开(公告)号：US07227261B2
公开(公告)日：2007-06-05
申请号：US10648164
申请日：2003-08-26
申请人： Larry D. Kinsman , Jerry M. Brooks , Warren M. Farnworth , Walter L. Moden , Terry R. Lee
发明人： Larry D. Kinsman , Jerry M. Brooks , Warren M. Farnworth , Walter L. Moden , Terry R. Lee
IPC分类号： H01L23/34
CPC分类号： H05K3/301 , H01L2924/0002 , Y10T29/4913 , H01L2924/00
摘要： A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. At least a portion of the semiconductor device may be exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. The alignment device may secure the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.
摘要翻译：一种可垂直安装的半导体器件组件，包括半导体器件和用于将半导体器件附着到载体衬底的机构。半导体器件的每个接合焊盘都设置在其单个边缘附近。可以暴露半导体器件的至少一部分。对准装置附接到载体基板。可垂直安装的半导体器件封装上的安装元件与对准装置接合以使半导体器件和对准器件互连。对准装置可以使垂直安装的半导体器件封装相对于载体衬底垂直地固定。接合焊盘和载体基板上的对应端子之间的距离非常小以减少阻抗。垂直安装的半导体器件封装也可以容易地用户升级。

46. 发明授权

US06963128B2 Vertically mountable and alignable semiconductor device assembly 失效
标题翻译：垂直安装和对准的半导体器件组件
公开(公告)号：US06963128B2
公开(公告)日：2005-11-08
申请号：US10352698
申请日：2003-01-27
申请人： Larry D. Kinsman , Walter L. Moden , Warren M. Farnworth
发明人： Larry D. Kinsman , Walter L. Moden , Warren M. Farnworth
IPC分类号： H01L25/10 , H05K3/30 , H01L23/48 , H01L23/52
CPC分类号： H05K3/301 , H01L25/105 , H01L2225/107 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K2201/10454 , H05K2201/10696 , Y10S83/942 , Y10T29/49121 , Y10T29/4913 , Y10T29/49135 , Y10T29/49147 , Y10T29/49156 , Y10T29/49169 , Y10T29/53174 , Y10T29/53178 , H01L2924/00
摘要： A vertically mountable semiconductor device including a plurality of stub contacts extending perpendicularly from a bottom edge thereof. A complementary alignment device includes a receptacle for receiving the vertically mountable semiconductor device. The alignment device is attachable to a carrier substrate. Upon attachment of the alignment device to a carrier substrate and insertion of a vertically mountable semiconductor device into the receptacle, a contact element applies a downward force to the vertically mountable semiconductor device to establish and maintain an electrical connection between the vertically mountable semiconductor device and the carrier substrate.
摘要翻译：一种可垂直安装的半导体器件，包括从其底部边缘垂直延伸的多个短截线触头。互补对准装置包括用于接收垂直安装的半导体器件的插座。对准装置可附接到载体基板。在将对准装置附接到载体基板并将可垂直安装的半导体装置插入到插座中时，接触元件向垂直安装的半导体器件施加向下的力，以建立并保持可垂直安装的半导体器件与载体衬底。

47. 发明授权

US06911737B2 Semiconductor device package and method 失效
标题翻译：半导体器件封装及方法
公开(公告)号：US06911737B2
公开(公告)日：2005-06-28
申请号：US09930295
申请日：2001-08-16
申请人： Alan G. Wood , Larry D. Kinsman
发明人： Alan G. Wood , Larry D. Kinsman
IPC分类号： H01L21/60 , H01L23/498 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/94 , H01L23/4985 , H01L24/16 , H01L24/31 , H01L24/45 , H01L24/48 , H01L24/97 , H01L2224/05599 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/73253 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01047 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2224/83 , H01L2924/00012 , H01L2924/013 , H01L2924/01028 , H01L2924/0105 , H01L2924/00013 , H01L2224/43
摘要： A method of making semiconductor device packages includes the steps of attaching a wafer to a dielectric layer, testing semiconductor devices in the wafer, and then dicing the layered assembly. The dielectric layer may be, for example, a flexible tape. The semiconductor devices may be chips containing integrated circuits or memory devices. The dicing operation may be performed by a circular saw or by another suitable apparatus. The chips may be connected to input/output devices, such as ball grid arrays, on the dielectric layer, before the testing and dicing steps. Full wafer testing may be-conducted through the ball grid arrays. A relatively stiff metal sheet may be included in the layered assembly before the testing and dicing steps. The metal material may be used as heat spreaders and/or as electrical ground planes. The chips may be connected to the ball grid arrays by wire bonds or flip chip bumps and vias through the dielectric layer. Alignment of the wafer with respect to the dielectric tape may be accomplished by an optical device or by a magnetic system.
摘要翻译：制造半导体器件封装的方法包括将晶片附着到电介质层，测试晶片中的半导体器件，然后切割层状组件的步骤。介电层可以是例如柔性带。半导体器件可以是包含集成电路或存储器件的芯片。切割操作可以通过圆锯或其他合适的装置进行。在测试和切割步骤之前，芯片可以连接到电介质层上的输入/输出设备，例如球栅阵列。全晶圆测试可以通过球栅阵列进行。在测试和切割步骤之前，可以在分层组件中包括相对硬的金属片。金属材料可以用作散热器和/或电接地平面。芯片可以通过引线键合或倒装芯片凸块和通孔穿过电介质层连接到球栅阵列。晶片相对于介质带的对准可通过光学装置或磁性系统实现。

48. 发明授权

US06906424B2 Semiconductor package and method producing same 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US06906424B2
公开(公告)日：2005-06-14
申请号：US10777582
申请日：2004-02-12
申请人： Larry D. Kinsman
发明人： Larry D. Kinsman
IPC分类号： H01L23/31 , H01L23/495 , H01L23/48
CPC分类号： H01L23/49575 , H01L23/3107 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/05599 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01079 , H01L2924/10162 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00015 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A semiconductor device package and method of fabricating same. The package includes a lead frame having a die paddle and a plurality of lead fingers. A first semiconductor die exhibiting a first size is adhered to the die paddle and is electrically coupled with one or more of the plurality of lead fingers. A second semiconductor die exhibiting a second size, different from the first size, is also adhered to the die paddle and is electrically coupled with one or more of the plurality of lead fingers. The first semiconductor die and the second semiconductor die each exhibit circuitry which is substantially identical in function. In one embodiment the first semiconductor die may be adhered to a first side of the die paddle while the second semiconductor die is adhered to an opposing side of the die paddle.
摘要翻译：一种半导体器件封装及其制造方法。该封装包括具有管芯焊盘和多个引线指的引线框架。具有第一尺寸的第一半导体管芯被粘附到管芯焊盘并且与多个引线指中的一个或多个电连接。具有与第一尺寸不同的第二尺寸的第二半导体管芯也粘附到管芯焊盘并且与多个引线指中的一个或多个电连接。第一半导体管芯和第二半导体管芯各自表现出功能基本相同的电路。在一个实施例中，第一半导体管芯可以粘附到管芯焊盘的第一侧，而第二半导体管芯粘附到管芯焊盘的相对侧。

49. 发明授权

US06894372B2 Tape under frame for lead frame IC package assembly 失效
标题翻译：用于引线框架IC封装组件的框架下方
公开(公告)号：US06894372B2
公开(公告)日：2005-05-17
申请号：US10290741
申请日：2002-11-07
申请人： David J. Corisis , Larry D. Kinsman , Jerry M. Brooks
发明人： David J. Corisis , Larry D. Kinsman , Jerry M. Brooks
IPC分类号： H01L23/495 , H05K5/02
CPC分类号： H01L23/49506 , H01L23/49544 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/45139 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor integrated circuit device, and method of manufacturing the same, having a conventional-type lead frame with the die paddle removed. In particular, the die paddle is replaced with a section of tape that is supported by the ends of the lead fingers. The semiconductor die is attached to the tape so that it may be wire bonded to the lead fingers. The tape contains at least one slot to allow for expansion and/or contraction of the tape due to various temperatures experienced during the manufacturing process so that the tape does not wrinkle or warp to alter the position of the die.
摘要翻译：一种半导体集成电路器件及其制造方法，具有去除了管芯焊盘的常规型引线框架。特别地，模具板被用引线指的端部支撑的一部分带替代。将半导体管芯附着到带子上，使其可以被引线接合到引线指。胶带包含至少一个槽，以允许由于在制造过程中经历的各种温度而导致的带的膨胀和/或收缩，使得带不会起皱或翘曲以改变模具的位置。

50. 发明授权

US06803656B2 Semiconductor device including combed bond pad opening 失效
标题翻译：半导体器件包括精梳接合焊盘开口
公开(公告)号：US06803656B2
公开(公告)日：2004-10-12
申请号：US09928478
申请日：2001-08-13
申请人： Warren M. Farnworth , Walter L. Moden , Larry D. Kinsman
发明人： Warren M. Farnworth , Walter L. Moden , Larry D. Kinsman
IPC分类号： H01L2329
CPC分类号： H01L24/72 , H01L23/32 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/12042 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device including bond pads disposed proximate an edge thereof, and an overcoat layer. The overcoat layer defines notches around each of the bond pads. The overcoat layer may be formed from a photoimageable material such as a photoimageable epoxy. The invention also includes an alignment device that secures the semiconductor device perpendicularly upon a carrier substrate. The alignment device includes intermediate conductive elements which correspond to the bond pads of the semiconductor device. Upon insertion of the semiconductor device into the alignment device, the notches facilitate alignment of the bond pads with their corresponding intermediate conductive elements. The intermediate conductive elements establish an electrical connection between the semiconductor device and the carrier substrate.
摘要翻译：一种半导体器件，包括靠近其边缘的接合焊盘和外涂层。外涂层在每个接合焊盘周围形成凹口。外涂层可以由可光成像的材料例如可光成像的环氧树脂形成。本发明还包括将半导体器件垂直地固定在载体衬底上的对准装置。对准装置包括对应于半导体器件的接合焊盘的中间导电元件。在将半导体器件插入到对准装置中时，凹口有助于键合焊盘与其对应的中间导电元件的对准。中间导电元件在半导体器件和载体衬底之间建立电连接。

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