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41. 发明申请

US20090251988A1 SYSTEM AND METHOD FOR PROVIDING A NON-POWER-OF-TWO BURST LENGTH IN A MEMORY SYSTEM 有权
标题翻译：用于在存储器系统中提供非功率的两个BURST长度的系统和方法
公开(公告)号：US20090251988A1
公开(公告)日：2009-10-08
申请号：US12061045
申请日：2008-04-02
申请人： Kyu-hyoun Kim , Paul W. Coteus , Warren E. Maule , Kenneth L. Wright
发明人： Kyu-hyoun Kim , Paul W. Coteus , Warren E. Maule , Kenneth L. Wright
IPC分类号： G11C8/00
CPC分类号： G11C5/00 , G11C7/1018
摘要： A memory system, memory interface device and method for a non-power-of-two burst length are provided. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length from a power-of-two value to insert an error-detecting code in a burst on data lines between the memory interface device and the plurality of memory devices.
摘要翻译：提供了一种用于非二次突发长度的存储器系统，存储器接口装置和方法。存储器系统包括具有非二次突发长度逻辑的多个存储器件和包括非二次突发长度生成逻辑的存储器接口器件。非功率二突发长度生成逻辑从两个功率值扩展突发长度，以将错误检测码插入到存储器接口设备和多个存储器件之间的数据线上的突发中。

42. 发明授权

US07587559B2 Systems and methods for memory module power management 失效
标题翻译：内存模块电源管理的系统和方法
公开(公告)号：US07587559B2
公开(公告)日：2009-09-08
申请号：US11463743
申请日：2006-08-10
申请人： Mark A. Brittain , Warren E. Maule , Karthick Rajamani , Eric E. Retter , Robert B. Tremaine
发明人： Mark A. Brittain , Warren E. Maule , Karthick Rajamani , Eric E. Retter , Robert B. Tremaine
IPC分类号： G06F12/00
CPC分类号： G11C5/143 , G06F1/3225 , G11C5/04 , G11C5/14 , G11C11/4072
摘要： Systems and methods for determining memory module power requirements in a memory system. Embodiments include a memory system with a physical memory and a memory controller. The physical memory includes a plurality of memory devices. The memory controller is in communication with the physical memory and has a logical memory for storing power usage characteristics associated with the physical memory. The power usage characteristics are generated in response to a current operating environment of the memory system.
摘要翻译：用于确定存储器系统中的存储器模块功率需求的系统和方法。实施例包括具有物理存储器和存储器控制器的存储器系统。物理存储器包括多个存储器件。存储器控制器与物理存储器通信，并且具有用于存储与物理存储器相关联的功率使用特性的逻辑存储器。响应于存储器系统的当前操作环境而产生功率使用特性。

43. 发明申请

US20090063784A1 System for Enhancing the Memory Bandwidth Available Through a Memory Module 有权
标题翻译：通过内存模块提高内存带宽的系统
公开(公告)号：US20090063784A1
公开(公告)日：2009-03-05
申请号：US11848309
申请日：2007-08-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： G06F13/4059 , G06F13/1684
摘要： A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory hub device integrated in a memory module. The memory system includes a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module. The memory system also includes a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module. In the memory system, the first set of memory devices are separate from the second set of memory devices. In the memory system, the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces.
摘要翻译：提供了一种存储器系统，其增强了通过存储器模块可用的存储器带宽。存储器系统包括集成在存储器模块中的存储器集线器设备。存储器系统包括集成在存储器集线器设备中的第一存储器设备数据接口，其与集成在存储器模块中的第一组存储器设备进行通信。存储器系统还包括集成在存储器集线器设备中的第二存储器设备数据接口，其与集成在存储器模块中的第二组存储器设备进行通信。在存储器系统中，第一组存储器件与第二组存储器件分开。在存储器系统中，第一和第二组存储器设备经由独立的第一和第二存储器件数据接口由存储器集线器设备进行通信。

44. 发明申请

US20090063729A1 System for Supporting Partial Cache Line Read Operations to a Memory Module to Reduce Read Data Traffic on a Memory Channel 有权
标题翻译：用于支持部分高速缓存行读取操作到内存模块以减少内存通道读取数据流量的系统
公开(公告)号：US20090063729A1
公开(公告)日：2009-03-05
申请号：US11848312
申请日：2007-08-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F3/00
CPC分类号： G06F13/28 , G06F11/1048 , G06F12/0879 , G06F12/0888 , G06F13/1684
摘要： A memory system is provided that supports partial cache line read operations to a memory module to reduce read data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub comprises burst logic integrated in the memory hub device. The burst logic determines an amount of read data to be transmitted from the set of memory devices and generates a burst length field corresponding to the amount of read data. The memory hub also comprises a memory hub controller integrated in the memory hub device. The memory hub controller controls the amount of read data that is transmitted using the burst length field. The memory hub device transmits the amount of read data that is equal to or less than a conventional data burst amount of data.
摘要翻译：提供了一种存储器系统，其支持对存储器模块的部分高速缓存行读取操作以减少存储器通道上的读取数据流量。存储器系统包括集成在存储器模块中的存储器集线器设备和耦合到存储器集线器设备的一组存储器设备。存储器集线器包括集成在存储器集线器设备中的突发逻辑。突发逻辑确定要从该组存储器件发送的读取数据量，并产生与读取数据量对应的突发长度字段。存储器集线器还包括集成在存储器集线器设备中的存储器集线器控制器。存储器集线器控制器控制使用突发长度字段发送的读取数据量。存储器集线器设备发送等于或小于常规数据突发数据量的读取数据量。

45. 发明授权

US07447831B2 Memory systems for automated computing machinery 有权
标题翻译：自动计算机的存储系统
公开(公告)号：US07447831B2
公开(公告)日：2008-11-04
申请号：US11383989
申请日：2006-05-18
申请人： Daniel M. Dreps , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
发明人： Daniel M. Dreps , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F13/14
CPC分类号： G06F13/1684 , G06F13/1673 , G06F13/1678 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer. Each memory buffer device in the first memory layer typically is connected to the outbound link to receive memory signals from the memory controller.
摘要翻译：公开了包括存储器控制器和与存储器控制器连接到出站链路的出站链路的存储器系统。出站链路通常包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器件的多个导电路径; 以及在第一存储器层中的至少两个存储缓冲器件。第一存储器层中的每个存储器缓冲器件通常连接到出站链路以从存储器控制器接收存储器信号。

46. 发明授权

US07441060B2 System, method and storage medium for providing a service interface to a memory system 有权
标题翻译：用于向存储器系统提供服务接口的系统，方法和存储介质
公开(公告)号：US07441060B2
公开(公告)日：2008-10-21
申请号：US10977921
申请日：2004-10-29
申请人： Kevin C. Gower , Warren E. Maule , Juergen Saalmueller
发明人： Kevin C. Gower , Warren E. Maule , Juergen Saalmueller
IPC分类号： G06F13/00
CPC分类号： G06F13/4243
摘要： A cascaded interconnect system for providing a service interface to a memory system. The cascaded interconnect system includes a master service interface module, a service interface bus, and one or more slave service interface modules. The master service interface module and the slave interface modules are cascade interconnected via the service interface bus. Each slave service interface module is in communication with a corresponding memory module for providing a service to the memory module.
摘要翻译：用于向存储器系统提供服务接口的级联互连系统。级联互联系统包括主服务接口模块，业务接口总线以及一个或多个从业务接口模块。主服务接口模块和从接口模块通过业务接口总线级联互联。每个从业务接口模块与相应的存储器模块通信，用于向存储器模块提供服务。

47. 发明申请

US20080177929A1 SYSTEM, METHOD AND STORAGE MEDIUM FOR A MEMORY SUBSYSTEM COMMAND INTERFACE 失效
标题翻译：用于记忆子系统命令界面的系统，方法和存储介质
公开(公告)号：US20080177929A1
公开(公告)日：2008-07-24
申请号：US12059164
申请日：2008-03-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F12/04
CPC分类号： G06F13/1684
摘要： A system for implementing a memory subsystem command interface, the system including a cascaded interconnect system including one or more memory modules, a memory controller and a memory bus. The memory controller generates a data frame that includes a plurality of commands. The memory controller and the memory module are interconnected by a packetized multi-transfer interface via the memory bus and the frame is transmitted to the memory modules via the memory bus.
摘要翻译：一种用于实现存储器子系统命令接口的系统，该系统包括包括一个或多个存储器模块，存储器控制器和存储器总线的级联互连系统。存储器控制器生成包括多个命令的数据帧。存储器控制器和存储器模块通过存储器总线通过分组化的多传输接口互连，并且帧经由存储器总线传送到存储器模块。

48. 发明授权

US07299313B2 System, method and storage medium for a memory subsystem command interface 失效
标题翻译：用于内存子系统命令界面的系统，方法和存储介质
公开(公告)号：US07299313B2
公开(公告)日：2007-11-20
申请号：US10977793
申请日：2004-10-29
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： G06F13/1684
摘要： A system for implementing a memory subsystem command interface, the system including a cascaded interconnect system including one or more memory modules, a memory controller and a memory bus. The memory controller generates a data frame that includes a plurality of commands. The memory controller and the memory module are interconnected by a packetized multi-transfer interface via the memory bus and the frame is transmitted to the memory modules via the memory bus.
摘要翻译：一种用于实现存储器子系统命令接口的系统，该系统包括包括一个或多个存储器模块，存储器控制器和存储器总线的级联互连系统。存储器控制器生成包括多个命令的数据帧。存储器控制器和存储器模块通过存储器总线通过分组化的多传输接口互连，并且帧经由存储器总线传送到存储器模块。

49. 发明授权

US5864686A Method for dynamic address coding for memory mapped commands directed to a system bus and/or secondary bused 失效
标题翻译：用于针对系统总线和/或辅助总线的存储器映射命令的动态地址编码的方法
公开(公告)号：US5864686A
公开(公告)日：1999-01-26
申请号：US751351
申请日：1996-11-19
申请人： John M. Kaiser , Warren E. Maule
发明人： John M. Kaiser , Warren E. Maule
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/404
摘要： In a data processing system including a system bus supporting memory mapped devices, dynamic response to a memory mapped command is achieved by receiving a status response from each device attached to the system bus and comparing a priority associated with each such status response to a predetermined priority. If a priority associated with the status response from one of the devices equals or exceeds the predetermined priority, indicating that the address in the memory mapped command is acknowledged in some form by that device, the status response from that device is forwarded to all devices attached to the system bus. If no status response received from the devices has an associated priority equalling or exceeding the predetermined priority, the address is acknowledged and the memory mapped command accepted and forwarded to a lower bus. If the memory mapped command is not accepted by the lower bus, dummy data is returned and a machine check is signaled.
摘要翻译：在包括支持存储器映射设备的系统总线的数据处理系统中，通过从附加到系统总线的每个设备接收状态响应并将与每个这样的状态响应相关联的优先级与预定优先级进行比较来实现对存储器映射命令的动态响应。如果与来自其中一个设备的状态响应相关联的优先级等于或超过预定优先级，指示存储器映射命令中的地址以某种形式被该设备确认，则来自该设备的状态响应被转发到所附接的所有设备到系统总线。如果没有从设备接收到的状态响应具有等于或超过预定优先级的相关联优先级，则确认地址并接受存储器映射命令并将其转发到较低总线。如果下层总线不接受存储器映射命令，则返回虚拟数据并发出机器检查。

50. 发明授权

US5516194A Combination child's seat and armrest for a vehicle 失效
标题翻译：组合儿童座椅和扶手用于车辆
公开(公告)号：US5516194A
公开(公告)日：1996-05-14
申请号：US273304
申请日：1994-07-11
申请人： Warren E. Maule
发明人： Warren E. Maule
IPC分类号： B60N2/06 , B60N2/30 , B60N2/34 , B60N2/75 , A47C7/46
CPC分类号： B60N2/06 , B60N2/062 , B60N2/3081 , B60N2/345 , B60N2/4673 , B60N2/468
摘要： A combination child's seat and armrest assembly includes an upper portion and lower portion. The portions are pivotably attached to each other at the front of the assembly, thereby providing for the raising and lowering of the upper portion. In this lowered position, the assembly functions as an armrest for the driver and passenger. In its raised position, a child may be seated facing front, or the bottom side of the raised upper portion. This positioning securely fits the child between the raised upper portion and the seat back of the vehicle's seat. A bed telescoping between the rear seat and the front seat may also be provided. A front bench seat includes three sections, two laterally movable end sections and a central backrest section. For entry into or exit from the back seat of the vehicle, one or the other of the end sections is moved inward toward the central section. The central section is comprised of a back half and a front half. On movement of one or the other of the sections inward toward the central sections, part of the front half moves away from the back half to allow space for entry of the moving section.
摘要翻译：组合儿童座椅和扶手组件包括上部和下部。这些部分在组件的前部可枢转地彼此附接，从而提供上部的升高和降低。在这种降低的位置，组件用作驾驶员和乘客的扶手。在其抬起的位置，一个孩子可以面向前部或者凸起的上部的底侧。该定位将孩子牢固地适配在车辆座椅的凸起的上部和座椅靠背之间。还可以设置在后座椅和前座椅之间伸缩的床。前台座椅包括三个部分，两个可横向移动的端部部分和中央靠背部分。为了进入或离开车辆的后座，一个或另一个端部部分朝向中心部分向内移动。中央部分由后半部分和前半部分组成。在一个或另一个部分朝向中央部分向内移动时，前半部分的一部分从后半部移动以允许移动部分进入的空间。

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