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41. 发明授权

US08327345B2 Computation table for block computation 有权
标题翻译：块计算的计算表
公开(公告)号：US08327345B2
公开(公告)日：2012-12-04
申请号：US12336332
申请日：2008-12-16
申请人： Ravi K. Arimilli , Balaram Sinharoy
发明人： Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F9/45
CPC分类号： G06F8/4441
摘要： In response to receiving pre-processed code, a compiler identifies a code section that is not candidate for acceleration and identifying a code block specifying an iterated operation that is a candidate for acceleration. In response to identifying the code section, the compiler generates post-processed code containing one or more lower level instructions corresponding to the identified code section, and in response to identifying the code block, the compiler creates and outputs an operation data structure separate from the post-processed code that identifies the iterated operation. The compiler places a block computation command in the post-processed code that invokes processing of the operation data structure to perform the iterated operation and outputs the post-processed code.
摘要翻译：响应于接收预处理的代码，编译器识别不是加速候选的代码段，并且识别指定作为加速候选的迭代操作的代码块。响应于识别代码部分，编译器生成包含与识别的代码部分相对应的一个或多个较低级别指令的后处理代码，并且响应于识别代码块，编译器创建并输出与标识迭代操作的后处理代码。编译器在后处理代码中放置块计算命令，该代码调用操作数据结构的处理以执行迭代操作，并输出后处理代码。

42. 发明授权

US08275963B2 Asynchronous memory move across physical nodes with dual-sided communication 有权
标题翻译：异步存储器通过双面通信跨物理节点移动
公开(公告)号：US08275963B2
公开(公告)日：2012-09-25
申请号：US12024486
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/08
CPC分类号： G06F12/1027 , G06F12/0811 , G06F12/084 , G06F12/0862
摘要： A distributed data processing system includes: (1) a first node with a processor, a first memory, and asynchronous memory mover logic; and connection mechanism that connects (2) a second node having a second memory. The processor includes processing logic for completing a cross-node asynchronous memory move (AMM) operation, wherein the processor performs a move of data in virtual address space from a first effective address to a second effective address, and the asynchronous memory mover logic completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address. The data is transmitted via the connection mechanism connecting the two nodes independent of the processor.
摘要翻译：分布式数据处理系统包括：（1）具有处理器的第一节点，第一存储器和异步存储器移动器逻辑; 以及连接机构，其连接（2）具有第二存储器的第二节点。处理器包括用于完成跨节点异步存储器移动（AMM）操作的处理逻辑，其中处理器执行将虚拟地址空间中的数据从第一有效地址移动到第二有效地址，并且异步存储器移动器逻辑完成从具有第一实际地址的第一存储器中的第一存储器位置的数据的物理移动到具有第二实际地址的第二存储器中的第二存储器位置。数据通过连接独立于处理器的两个节点的连接机制进行传输。

43. 发明授权

US07958327B2 Performing an asynchronous memory move (AMM) via execution of AMM store instruction within the instruction set architecture 有权
标题翻译：通过在指令集体系结构中执行AMM存储指令来执行异步存储器移动（AMM）
公开(公告)号：US07958327B2
公开(公告)日：2011-06-07
申请号：US12024494
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/26 , G06F9/34
CPC分类号： G06F9/30032 , G06F12/0831 , G06F12/0862 , G06F12/10
摘要： A data processing system with a processor and memory includes an instruction set architecture (ISA) that provides an asynchronous memory move (AMM) store (ST) instruction. When the processor executes the AMM ST instruction, the processor performs a series of functions, which initiates an asynchronous memory move (AMM) operation. The AMM ST instruction moves data from a first memory location having a first real address to a second memory location having a second real address by: (a) performing a move of the data in virtual address space utilizing a source effective address that is memory mapped to the first memory location and a destination effective address that is memory mapped to the second memory location. When the move is completed in the virtual address space, the AMM operation performs the physical move of the data to the second memory location outside the processor core, without processor involvement.
摘要翻译：具有处理器和存储器的数据处理系统包括提供异步存储器移动（AMM）存储（ST）指令的指令集架构（ISA）。当处理器执行AMM ST指令时，处理器执行一系列功能，其启动异步存储器移动（AMM）操作。 AMM ST指令通过以下方式将数据从具有第一实际地址的第一存储器位置移动到具有第二实际地址的第二存储器位置：（a）使用存储器映射的源有效地址来执行虚拟地址空间中的数据移动到第一存储器位置和存储器映射到第二存储器位置的目的地有效地址。当在虚拟地址空间中完成移动时，AMM操作将数据物理移动到处理器核心外部的第二存储器位置，而无需处理器参与。

44. 发明授权

US07941627B2 Specialized memory move barrier operations 失效
标题翻译：专业记忆移动屏障操作
公开(公告)号：US07941627B2
公开(公告)日：2011-05-10
申请号：US12024674
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/30043 , G06F9/30087
摘要： An instruction set architecture (ISA) includes an asynchronous memory move (AMM) synchronization (SYNC) instruction. When processor of a data processing system executes the AMM SYNC instruction, the processor prevents an AMM operation generated by a subsequently received/executed AMM ST instruction from proceeding with the data move portion of the AMM operation within the memory subsystem until completion of all ongoing memory access operations within the memory subsystem and fabric. The AMM operation does not wait for a normal barrier operation. The processor forwards the information relevant to initiate the AMM operation to an asynchronous memory mover logic, and signals the logic to not proceed with the AMM operation until signaled of the completion of the AMM SYNC.
摘要翻译：指令集架构（ISA）包括异步存储器移动（AMM）同步（SYNC）指令。当数据处理系统的处理器执行AMM SYNC指令时，处理器防止随后接收/执行的AMM ST指令产生的AMM操作进入存储器子系统内的AMM操作的数据移动部分，直到完成所有正在进行的存储器内存子系统和结构中的访问操作。 AMM操作不等待正常的屏障操作。处理器将与启动AMM操作相关的信息转发到异步存储器移动器逻辑，并且将逻辑信号发送到不进行AMM操作，直到AMM SYNC完成为止。

45. 发明申请

US20100153681A1 Block Driven Computation With An Address Generation Accelerator 失效
标题翻译：使用地址生成加速器进行块驱动计算
公开(公告)号：US20100153681A1
公开(公告)日：2010-06-17
申请号：US12336315
申请日：2008-12-16
申请人： Ravi K. Arimilli , Balaram Sinharoy
发明人： Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F9/34 , G06F12/02
CPC分类号： G06F9/383 , G06F9/30094 , G06F9/345
摘要： A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit, an instruction sequencing unit that fetches instructions for execution by the at least one execution unit, and an address generation accelerator. The address generation accelerator, responsive to an initiation signal received from the instruction sequencing unit, computes and outputs first and second effective addresses of operands of an operation.
摘要翻译：处理器包括执行指令的至少一个执行单元，耦合到所述至少一个执行单元的至少一个寄存器文件，其缓冲由所述至少一个执行单元访问的操作数，指令排序单元，其通过所述至少一个执行单元和地址生成加速器。地址产生加速器响应于从指令排序单元接收的发起信号，计算并输出操作的操作数的第一和第二有效地址。

46. 发明申请

US20100153648A1 Block Driven Computation Using A Caching Policy Specified In An Operand Data Structure 有权
标题翻译：使用操作数据结构中指定的缓存策略进行块驱动计算
公开(公告)号：US20100153648A1
公开(公告)日：2010-06-17
申请号：US12336350
申请日：2008-12-16
申请人： Ravi K. Arimilli , Balaram Sinharoy
发明人： Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F2212/6028
摘要： A processor has an associated memory hierarchy including a cache memory. The processor includes an instruction sequencing unit that fetches instructions for processing, an operand data structure including a plurality of entries corresponding to operands of operations to be performed by the processor, and a computation engine. A first entry among the plurality of entries in the operand data structure specifies a first caching policy for a first operand, and a second entry specifies a second caching policy for a second operand. The computation engine computes and stores operands in the memory hierarchy in accordance with the cache policies indicated within the operand data structure.
摘要翻译：处理器具有包括高速缓冲存储器的相关联的存储器层级。所述处理器包括：指令排序单元，其提取用于处理的指令;操作数数据结构，包括与由所述处理器执行的操作操作数对应的多个条目;以及计算引擎。操作数数据结构中的多个条目中的第一条目指定第一操作数的第一高速缓存策略，第二条目指定用于第二操作数的第二高速缓存策略。计算引擎根据操作数数据结构中指示的缓存策略计算并存储存储器层次结构中的操作数。

47. 发明申请

US20090198955A1 ASYNCHRONOUS MEMORY MOVE ACROSS PHYSICAL NODES (DUAL-SIDED COMMUNICATION FOR MEMORY MOVE) 有权
标题翻译：异常记忆移动物理名称（双面通信用于记忆移动）
公开(公告)号：US20090198955A1
公开(公告)日：2009-08-06
申请号：US12024486
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F15/167 , G06F12/00
CPC分类号： G06F12/1027 , G06F12/0811 , G06F12/084 , G06F12/0862
摘要： A distributed data processing system includes: (1) a first node with a processor, a first memory, and asynchronous memory mover logic; and connection mechanism that connects (2) a second node having a second memory. The processor includes processing logic for completing a cross-node asynchronous memory move (AMM) operation, wherein the processor performs a move of data in virtual address space from a first effective address to a second effective address, and the asynchronous memory mover logic completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address. The data is transmitted via the connection mechanism connecting the two nodes independent of the processor.
摘要翻译：分布式数据处理系统包括：（1）具有处理器的第一节点，第一存储器和异步存储器移动器逻辑; 以及连接机构，其连接（2）具有第二存储器的第二节点。处理器包括用于完成跨节点异步存储器移动（AMM）操作的处理逻辑，其中处理器执行将虚拟地址空间中的数据从第一有效地址移动到第二有效地址，并且异步存储器移动器逻辑完成从具有第一实际地址的第一存储器中的第一存储器位置的数据的物理移动到具有第二实际地址的第二存储器中的第二存储器位置。数据通过连接独立于处理器的两个节点的连接机制进行传输。

48. 发明申请

US20090198934A1 FULLY ASYNCHRONOUS MEMORY MOVER 失效
标题翻译：充分的异常记忆运动
公开(公告)号：US20090198934A1
公开(公告)日：2009-08-06
申请号：US12024613
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/02 , G06F12/14 , G06F9/46
CPC分类号： G06F9/30032 , G06F12/0831 , G06F12/0862 , G06F12/10
摘要： A data processing system has a processor and a memory coupled to the processor and an asynchronous memory mover coupled to the processor. The asynchronous memory mover has registers for receiving a set of parameters from the processor, which parameters are associated with an asynchronous memory move (AMM) operation initiated by the processor in virtual address space, utilizing a source effective address and a destination effective address. The asynchronous memory mover performs the AMM operation to move the data from a first physical memory location having a source real address corresponding to the source effective address to a second physical memory location having a destination real address corresponding to the destination effective address. The asynchronous memory mover has an associated off-chip translation mechanism. The AMM operation thus occurs independent of the processor, and the processor continues processing other operations independent of the AMM operation.
摘要翻译：数据处理系统具有耦合到处理器的处理器和存储器以及耦合到处理器的异步存储器移动器。异步存储器移动器具有用于从处理器接收一组参数的寄存器，这些参数与虚拟地址空间中由处理器发起的异步存储器移动（AMM）操作相关联，利用源有效地址和目的地有效地址。异步存储器移动器执行AMM操作以将来自具有与源有效地址相对应的源实际地址的第一物理存储器位置的数据移动到具有与目的地有效地址相对应的目的地实际地址的第二物理存储器位置。异步存储器移动器具有相关的片外转换机制。因此，AMM操作独立于处理器，并且处理器继续处理独立于AMM操作的其他操作。

49. 发明申请

US20090198917A1 SPECIALIZED MEMORY MOVE BARRIER OPERATIONS 失效
标题翻译：专用记忆移动障碍操作
公开(公告)号：US20090198917A1
公开(公告)日：2009-08-06
申请号：US12024674
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F9/00
CPC分类号： G06F9/3834 , G06F9/30043 , G06F9/30087
摘要： An instruction set architecture (ISA) includes an asynchronous memory move (AMM) synchronization (SYNC) instruction. When processor of a data processing system executes the AMM SYNC instruction, the processor prevents an AMM operation generated by a subsequently received/executed AMM ST instruction from proceeding with the data move portion of the AMM operation within the memory subsystem until completion of all ongoing memory access operations within the memory subsystem and fabric. The AMM operation does not wait for a normal barrier operation. The processor forwards the information relevant to initiate the AMM operation to an asynchronous memory mover logic, and signals the logic to not proceed with the AMM operation until signaled of the completion of the AMM SYNC.
摘要翻译：指令集架构（ISA）包括异步存储器移动（AMM）同步（SYNC）指令。当数据处理系统的处理器执行AMM SYNC指令时，处理器防止随后接收/执行的AMM ST指令产生的AMM操作进入存储器子系统内的AMM操作的数据移动部分，直到完成所有正在进行的存储器内存子系统和结构中的访问操作。 AMM操作不等待正常的屏障操作。处理器将与启动AMM操作相关的信息转发到异步存储器移动器逻辑，并且将逻辑信号发送到不进行AMM操作，直到AMM SYNC完成为止。

50. 发明申请

US20090198897A1 CACHE MANAGEMENT DURING ASYNCHRONOUS MEMORY MOVE OPERATIONS 有权
标题翻译：非正常记忆移动操作期间的缓存管理
公开(公告)号：US20090198897A1
公开(公告)日：2009-08-06
申请号：US12024526
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3017 , G06F9/3877 , G06F12/10
摘要： A data processing system includes a mechanism for completing an asynchronous memory move (AMM) operation in which the processor receives an AMM ST instruction and processes a processor-level move of data in virtual address space and an asynchronous memory mover then completes a physical move of the data within the real address space (memory). A status/control field of the AMM ST instruction includes an indication of a requested treatment of the lower level cache(s) on completion of the AMM operation. When the status/control field indicates an update to at least one cache should be performed, the asynchronous memory mover automatically forwards a copy of the data from the data move to the lower level cache, and triggers an update of a coherency state for a cache line in which the copy of the data is placed.
摘要翻译：数据处理系统包括用于完成异步存储器移动（AMM）操作的机制，其中处理器接收AMM ST指令并处理虚拟地址空间中的数据的处理器级移动，然后异步存储器移动器完成物理移动实际地址空间（内存）中的数据。 AMM ST指令的状态/控制字段在完成AMM操作时包括对低级缓存的请求处理的指示。当状态/控制字段指示应该执行至少一个缓存的更新时，异步存储器移动器自动将数据的副本从数据移动转发到较低级的高速缓存，并触发高速缓存的一致性状态的更新其中放置数据副本的行。

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