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41. 发明授权

US06576487B1 Method to distinguish an STI outer edge current component with an STI normal current component 失效
标题翻译：区分STI外缘电流分量与STI正常电流分量的方法
公开(公告)号：US06576487B1
公开(公告)日：2003-06-10
申请号：US10126363
申请日：2002-04-19
申请人： Zhigang Wang , Harpreet Kaur Sachar , Kuo-Tung Chang
发明人： Zhigang Wang , Harpreet Kaur Sachar , Kuo-Tung Chang
IPC分类号： G01R3126
CPC分类号： H01L22/34 , H01L21/76229 , H01L21/76232
摘要： The present invention details a method which characterizes an STI fabrication process, and more particularly provides information relating to a variation in the STI sidewall profile between trenches in a middle portion of an array and a trench on an outer portion thereof. The method comprises forming two STI arrays with an STI fabrication process, forming a conductive layer over each array, biasing each conductive layer and determining a current associated therewith. The two current are then utilized to ascertain the variation of interest.
摘要翻译：本发明详细描述了一种表征STI制造工艺的方法，并且更具体地提供了与阵列的中间部分中的沟槽和其外部部分上的沟槽之间的STI侧壁轮廓变化有关的信息。该方法包括用STI制造工艺形成两个STI阵列，在每个阵列上形成导电层，偏置每个导电层并确定与之相关联的电流。然后利用两个电流来确定兴趣的变化。

42. 发明授权

US5981340A Method of building an EPROM cell without drain disturb and reduced select gate resistance 失效
标题翻译：构建EPROM单元而无漏极干扰和降低选择栅极电阻的方法
公开(公告)号：US5981340A
公开(公告)日：1999-11-09
申请号：US939397
申请日：1997-09-29
申请人： Kuo-Tung Chang , Erwin J. Prinz , Craig T. Swift
发明人： Kuo-Tung Chang , Erwin J. Prinz , Craig T. Swift
IPC分类号： G11C16/04 , H01L27/115 , H01L21/336
CPC分类号： H01L27/115 , G11C16/0433
摘要： A semiconductor device (70) includes a memory cell having a select transistor (67) and a storage transistor (65) having a relatively uniform tunnel dielectric thickness under both the floating gate (651) of the storage transistor and the select gate (671) of the select transistor (67). The select transistor (67) is adjacent to the drain region (68) for the memory cell to nearly eliminate a drain disturb problem. During programming, the control gate (652) is at a negative potential, and the drain region (68) is at a positive potential. The drain potential is sufficiently low to not degrade the tunnel dielectric layer (42) of the select transistor (67). During erase, a positive potential is applied to the control gate (652). The relatively uniform tunnel dielectric layer (42) thickness of the select transistor (67) allows for a faster operating device by increasing the read current of the memory device.
摘要翻译：半导体器件（70）包括具有在存储晶体管的浮动栅极（651）和选择栅极（671）两者下具有相对均匀的隧道电介质厚度的选择晶体管（67）和存储晶体管（65）的存储单元，的选择晶体管（67）。选择晶体管（67）与用于存储单元的漏极区域（68）相邻，几乎消除了漏极干扰问题。在编程期间，控制栅极（652）处于负电位，漏区（68）处于正电位。漏极电位足够低以不降低选择晶体管（67）的隧道介电层（42）。在擦除期间，向控制栅极施加正电位（652）。选择晶体管（67）的相对均匀的隧道介电层（42）的厚度通过增加存储器件的读取电流而允许更快的操作器件。

43. 发明授权

US5585293A Fabrication process for a 1-transistor EEPROM memory device capable of low-voltage operation 失效
标题翻译：能够进行低电压工作的1晶体管EEPROM存储器件的制造工艺
公开(公告)号：US5585293A
公开(公告)日：1996-12-17
申请号：US446133
申请日：1995-05-22
申请人： Umesh Sharma , Kuo-Tung Chang
发明人： Umesh Sharma , Kuo-Tung Chang
IPC分类号： H01L21/8247
CPC分类号： H01L27/11517
摘要： A method for fabricating a 1-transistor EEPROM device, which can be programmed and erased by Fowler-Nordheim tunneling includes the formation of a memory gate (28) overlying a tunneling region (22), and aligning source (32) and drain (34) regions in a semiconductor substrate (10), such that a vertically oriented electric field (46) is created in the tunneling region (22). The memory gate (28) is coupled to a contact region (30) by a connecting portion (31). A select gate (14) controls a portion of the channel region in the substrate (10) adjacent to the tunneling region (22). The EEPROM device is programmed by applying a voltage of a first polarity memory gate (28), while applying a voltage of a second polarity to the source region (32), the drain region (34), and to the substrate (10). Under the applied voltages, charge carriers tunnel through a tunnel oxide layer (40) and into a silicon nitride layer (42), located intermediate to the memory gate (28) and the tunnel region (22). To erase the EEPROM device, the polarity of the applied voltages is reversed, and charge carriers of an opposite conductivity type tunnel into the silicon nitride layer (42).
摘要翻译：可以由Fowler-Nordheim隧道编程和擦除的用于制造1-晶体管EEPROM器件的方法包括形成覆盖隧道区域（22）的存储栅极（28），以及对准源极（32）和漏极（34））区域，使得在隧道区域（22）中产生垂直取向的电场（46）。存储器栅极（28）通过连接部分（31）耦合到接触区域（30）。选择栅极（14）控制与隧道区域（22）相邻的衬底（10）中的沟道区域的一部分。通过施加第一极性存储栅极（28）的电压，同时向源极区域（32），漏极区域（34）和衬底（10）施加第二极性的电压来对EEPROM器件进行编程。在施加的电压下，电荷载流子穿过隧道氧化物层（40）并且位于位于存储器栅极（28）和隧道区域（22）中间的氮化硅层（42）中。为了擦除EEPROM器件，施加的电压的极性反转，并且反向导电型隧道的电荷载流子进入氮化硅层（42）。

44. 发明授权

US5498559A Method of making a nonvolatile memory device with five transistors 失效
标题翻译：制造具有五个晶体管的非易失性存储器件的方法
公开(公告)号：US5498559A
公开(公告)日：1996-03-12
申请号：US262167
申请日：1994-06-20
申请人： Kuo-Tung Chang
发明人： Kuo-Tung Chang
IPC分类号： G11C11/56 , G11C16/04 , H01L21/8247
CPC分类号： H01L27/11517 , G11C11/5621 , G11C16/0458
摘要： A nonvolatile memory includes five transistors. The memory has an MOS transistor in series with two pairs of transistors, where each pair includes a floating gate transistor and a metal-oxide-semiconductor transistor electrically connected in parallel. The memory structure may be formed with three levels of silicon-containing or metal-containing layers. The memory structure is less susceptible to read disturb errors compared to a prior art dual-bit nonvolatile memory structure.
摘要翻译：非易失性存储器包括五个晶体管。存储器具有与两对晶体管串联的MOS晶体管，其中每对晶体管包括并联电连接的浮栅晶体管和金属氧化物半导体晶体管。存储器结构可以由三层含硅或含金属层形成。与现有技术的双位非易失性存储器结构相比，存储器结构不易受读取干扰的影响。

45. 发明授权

US5494838A Process of making EEPROM memory device having a sidewall spacer floating gate electrode 失效
标题翻译：制造具有侧壁间隔物浮栅电极的EEPROM存储器件的工艺
公开(公告)号：US5494838A
公开(公告)日：1996-02-27
申请号：US448096
申请日：1995-05-23
申请人： Kuo-Tung Chang , Umesh Sharma , Jack Higman
发明人： Kuo-Tung Chang , Umesh Sharma , Jack Higman
IPC分类号： H01L27/115 , H01L29/423 , H01L21/8247
CPC分类号： H01L27/115 , H01L29/42324 , H01L29/42328
摘要： An EEPROM memory array includes a plurality of memory cells having a floating gate electrode (22) formed as a sidewall spacer adjacent to a control gate electrode (20). Source and drain regions (12, 14) reside in a semiconductor substrate (10) and define a segmented channel region (16) therebetween. A select gate electrode (18) overlies a first channel region (24) and separates the floating gate electrode (2) from the source region (12). The control gate electrode (20) overlies a third channeI region (28) and separates the floating gate electrode (22) from the drain region (14). The floating gate electrode (22) overlies a second channel region (26) and is separated therefrom by a thin tunnel oxide layer (42). The EEPROM device of the invention can be programmed by either source side injection, or by Fowler-Nordheim tunneling. Additionally, a process is provided for the fabrication of an EEPROM array utilizing adjacent select gate electrodes (18, 18') as a doping mask.
摘要翻译： EEPROM存储器阵列包括具有形成为与控制栅极（20）相邻的侧壁间隔的浮栅电极（22）的多个存储单元。源极和漏极区域（12,14）驻留在半导体衬底（10）中并且在它们之间限定分割的沟道区域（16）。选择栅电极（18）覆盖在第一沟道区（24）上，并将浮栅电极（2）与源极区（12）分离。控制栅电极（20）覆盖第三通道区域（28），并将浮栅电极（22）与漏极区域（14）分离。浮栅电极（22）覆盖第二沟道区（26），并由薄隧道氧化物层（42）分离。本发明的EEPROM装置可以通过源侧注入或通过Fowler-Nordheim隧道进行编程。此外，提供了一种制造使用相邻的选择栅电极（18,18'）作为掺杂掩模的EEPROM阵列的工艺。

46. 发明授权

US5408115A Self-aligned, split-gate EEPROM device 失效
标题翻译：自对准，分闸门EEPROM器件
公开(公告)号：US5408115A
公开(公告)日：1995-04-18
申请号：US223395
申请日：1994-04-04
申请人： Kuo-Tung Chang
发明人： Kuo-Tung Chang
IPC分类号： H01L27/115 , H01L29/792 , H01L27/12
CPC分类号： H01L29/792 , H01L27/115 , Y10S257/90
摘要： An EEPROM device capable of operating with a single low-voltage power supply includes a control gate electrode (30) and a select gate electrode (14) overlying separate portions of a channel region (32). Electrical charge is stored in an ONO layer (20) overlying a portion of the channel region (32) and separating the control gate electrode (30) from the channel region (32). The memory device is programmed using source-side injection, where electrons traverse the channel region (32) and are injected into trapping sites (34) located within the silicon nitride layer (24) of the ONO layer (20). To provide the necessary field gradient within the channel region (32), the control gate electrode (30) is spaced apart from the source region (16) by the select gate electrode (14). In either of two embodiments, two layers of polysilicon are used to form the select gate electrode (14) and the control gate electrode (30). The second layer of polysilicon is formed as a sidewall spacer on the first layer of polysilicon. Accordingly, a high-density memory device is achieved.
摘要翻译：能够使用单个低压电源操作的EEPROM器件包括覆盖沟道区域（32）的分离部分的控制栅电极（30）和选择栅电极（14）。电荷存储在覆盖通道区域（32）的一部分上的ONO层（20）中，并将控制栅电极（30）与沟道区域（32）分离。使用源侧注入对存储器件进行编程，其中电子穿过沟道区（32）并被注入到位于ONO层（20）的氮化硅层（24）内的俘获位置（34）中。为了在通道区域（32）内提供必要的场梯度，控制栅电极（30）通过选择栅电极（14）与源极区域（16）间隔开。在两个实施例中的任一个中，使用两层多晶硅来形成选择栅电极（14）和控制栅电极（30）。第二层多晶硅形成为第一层多晶硅上的侧壁间隔物。因此，实现了高密度存储器件。

47. 发明授权

US08587049B2 Memory cell system with charge trap 有权
标题翻译：带电荷陷阱的记忆体系统
公开(公告)号：US08587049B2
公开(公告)日：2013-11-19
申请号：US11458046
申请日：2006-07-17
申请人： Meng Ding , Amol Ramesh Joshi , Lei Xue , Takashi Orimoto , Kuo-Tung Chang
发明人： Meng Ding , Amol Ramesh Joshi , Lei Xue , Takashi Orimoto , Kuo-Tung Chang
IPC分类号： H01L29/76
CPC分类号： H01L27/11563 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/513 , H01L29/792
摘要： A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.
摘要翻译：提供一种存储单元系统，在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，在电荷陷阱层上形成中间层，并与中间层形成第二绝缘体层。

48. 发明授权

US08367537B2 Flash memory cell with a flair gate 有权
标题翻译：闪存单元，带有风格门
公开(公告)号：US08367537B2
公开(公告)日：2013-02-05
申请号：US11801823
申请日：2007-05-10
申请人： Meng Ding , YouSeok Suh , Shenqing Fang , Kuo-Tung Chang
发明人： Meng Ding , YouSeok Suh , Shenqing Fang , Kuo-Tung Chang
IPC分类号： H01L21/283
CPC分类号： H01L29/788 , H01L21/28273 , H01L21/28282 , H01L21/762 , H01L21/76224 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/792
摘要： An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width.
摘要翻译：本发明的实施例涉及一种形成存储单元的方法。该方法包括蚀刻衬底中的沟槽并用氧化物填充沟槽以形成浅沟槽隔离（STI）区域。与STI区域接触的衬底的有源区域的一部分形成位线STI边缘。该方法还包括在衬底的有源区上方和STI区上形成栅极结构。栅极结构具有基本上在衬底的有源区域的中心上方的第一宽度和基本上位于STI边缘的第二宽度，并且第二宽度大于第一宽度。

49. 发明授权

US08133801B1 Method for forming a semiconducting layer with improved gap filling properties 有权
标题翻译：用于形成具有改善的间隙填充性能的半导体层的方法
公开(公告)号：US08133801B1
公开(公告)日：2012-03-13
申请号：US11189875
申请日：2005-07-27
申请人： Rinji Sugino , Yider Wu , Minh Van Ngo , Jeffrey Sinclair Glick , Kuo-Tung Chang
发明人： Rinji Sugino , Yider Wu , Minh Van Ngo , Jeffrey Sinclair Glick , Kuo-Tung Chang
IPC分类号： H01L21/20
CPC分类号： H01L21/02532 , H01L21/0237 , H01L21/02488 , H01L21/02595 , H01L21/0262 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568
摘要： A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.
摘要翻译：一种制造存储器件的方法包括在衬底上形成第一介电层，在第一介电层上形成电荷存储元件，并在电荷存储元件上形成栅极间电介质。该方法还包括使用含氯的反应物在栅极间电介质上沉积硅控制栅极层。

50. 发明授权

US08114736B2 Integrated circuit system with memory system 有权
标题翻译：具有存储系统的集成电路系统
公开(公告)号：US08114736B2
公开(公告)日：2012-02-14
申请号：US11958254
申请日：2007-12-17
申请人： Simon Siu-Sing Chan , Hidehiko Shiraiwa , Kuo-Tung Chang , Angela T. Hui
发明人： Simon Siu-Sing Chan , Hidehiko Shiraiwa , Kuo-Tung Chang , Angela T. Hui
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11521
摘要： A method for forming an integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a barrier metal layer over the spacer, and forming a metal plug over the outer doped region and the barrier metal layer.
摘要翻译：提供了一种用于形成集成电路系统的方法，包括形成具有衬底的间隔物的存储部分，在衬底中形成存储部分的外部掺杂区域，在间隔物上形成阻挡金属层，并形成金属插塞外部掺杂区域和阻挡金属层。

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