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41. 发明申请

US20120292768A1 VIA/CONTACT AND DAMASCENE STRUCTURES 有权
标题翻译：威盛/联系人和大马士革结构
公开(公告)号：US20120292768A1
公开(公告)日：2012-11-22
申请号：US13563495
申请日：2012-07-31
申请人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Jung-Chih Tsao , Yu-Sheng Wang
发明人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Jung-Chih Tsao , Yu-Sheng Wang
IPC分类号： H01L23/52
CPC分类号： H01L21/76831 , H01L21/7684
摘要： A semiconductor structure is provided and includes a dielectric layer disposed over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is disposed in the opening.
摘要翻译：提供半导体结构，并且包括设置在基板上的电介质层。在电介质层上形成第一非导电阻挡层。通过第一非导电阻挡层和介电层内形成至少一个开口。在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上的开幕。种子层和导电层设置在开口中。

42. 发明申请

US20080251889A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080251889A1
公开(公告)日：2008-10-16
申请号：US11733897
申请日：2007-04-11
申请人： Jung-Chih Tsao , Yu-Sheng Wang , Kei-Wei Chen , Ying-Lang Wang
发明人： Jung-Chih Tsao , Yu-Sheng Wang , Kei-Wei Chen , Ying-Lang Wang
IPC分类号： H01L29/00
CPC分类号： H01L27/0805 , H01L28/60 , H01L28/75
摘要： A semiconductor device is disclosed. The device includes a substrate, a first metal layer, a dielectric layer, and a second metal layer. The first metal layer comprises a body-centered cubic lattice metal, and overlies the substrate. The dielectric layer overlies the first metal layer. The second metal layer overlies the dielectric layer.
摘要翻译：公开了一种半导体器件。该器件包括衬底，第一金属层，电介质层和第二金属层。第一金属层包括体心立方晶格金属，并且覆盖在基底上。电介质层覆盖在第一金属层上。第二金属层覆盖在电介质层上。

43. 发明授权

US07304728B2 Test device and method for laser alignment calibration 有权
标题翻译：用于激光对准校准的测试装置和方法
公开(公告)号：US07304728B2
公开(公告)日：2007-12-04
申请号：US10942554
申请日：2004-09-15
申请人： Shih-Tzung Chang , Yu-Ku Lin , Shih-Ho Lin , Kei-Wei Chen , Ting-Chun Wang , Ching-Hwan Su , Ying-Lang Wang
发明人： Shih-Tzung Chang , Yu-Ku Lin , Shih-Ho Lin , Kei-Wei Chen , Ting-Chun Wang , Ching-Hwan Su , Ying-Lang Wang
IPC分类号： G01C1/00
CPC分类号： H01L22/34 , G01B21/042
摘要： A novel test device and method for calibrating the alignment of a laser beam emitted from a laser metrology tool with respect to a target area on a substrate. The test device includes a laser-sensitive material having a calibration pattern that includes a target point. When the tool is properly adjusted, the laser beam strikes the target point and is released to production. If the laser beam misses the target point, the tool is re-adjusted and re-tested until the laser beam strikes the target point.
摘要翻译：一种用于校准从激光计量工具发射的激光束相对于衬底上的目标区域的对准的新型测试装置和方法。测试装置包括具有包括目标点的校准图案的激光敏感材料。当工具被正确调整时，激光束撞击目标点并释放到生产中。如果激光束错过目标点，则重新调整工具并重新测试直到激光束撞击目标点。

44. 发明申请

US20070257366A1 Barrier layer for semiconductor interconnect structure 审中-公开
标题翻译：半导体互连结构的阻挡层
公开(公告)号：US20070257366A1
公开(公告)日：2007-11-08
申请号：US11416945
申请日：2006-05-03
申请人： Yu-Sheng Wang , Jung-Chih Tsao , Kei-Wei Chen , Shih-Chieh Chang , Ying-Lang Wang
发明人： Yu-Sheng Wang , Jung-Chih Tsao , Kei-Wei Chen , Shih-Chieh Chang , Ying-Lang Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76846 , H01L21/76844 , H01L21/76865
摘要： A method for producing a semiconductor-device having an electrical interconnect. The method produces having an improved barrier layer between the interconnect conductor and the dielectric material in which the interconnect recess is formed. A dielectric layer is formed on top of a wafer substrate having at least one contact region. An interconnect for servicing the contact region is fabricated by forming an interconnect recess and then depositing a primary barrier layer of tantalum nitride and subjecting it to a re-sputtering operation. A film layer of tantalum is then deposited and re-sputtered. Following this operation, a seed layer is formed, and then a conductor is used to fill the interconnect recess. Planerizing the surface of the wafer so that further fabrication may be performed may complete the process.
摘要翻译：一种具有电互连的半导体器件的制造方法。该方法产生在互连导体和形成有互连凹槽的电介质材料之间具有改进的阻挡层。在具有至少一个接触区域的晶片衬底的顶部上形成电介质层。通过形成互连凹槽然后沉积氮化钽的主阻挡层并对其进行再溅射操作来制造用于维护接触区域的互连。然后沉积钽薄膜层并重新溅射。在该操作之后，形成种子层，然后使用导体来填充互连凹槽。使晶片的表面平整化，以便进一步制造可以完成该工艺。

45. 发明申请

US20060086609A1 Current-leveling electroplating/electropolishing electrode 有权
标题翻译：电流调平电镀/电解抛光电极
公开(公告)号：US20060086609A1
公开(公告)日：2006-04-27
申请号：US10971836
申请日：2004-10-22
申请人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Shih-Ho Lin , Chun-Chang Chen
发明人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Shih-Ho Lin , Chun-Chang Chen
IPC分类号： C25B11/02
CPC分类号： H01L21/2885 , C25D17/001 , C25D17/12 , Y10T29/49208 , Y10T29/53204
摘要： A current-leveling electrode for improving electroplating and electrochemical polishing uniformity in the electrochemical plating or electropolishing of metals on a substrate is disclosed. The current-leveling electrode includes a base electrode and at least one sub-electrode carried by the base electrode. The at least one sub-electrode has a width which is less than a width of the base electrode to impart a generally tapered, stepped or convex configuration to the current-leveling electrode.
摘要翻译：公开了一种用于改善电化学电镀中的电镀和电化学抛光均匀性的电流调节电极或对基底上的金属的电解抛光。电流调平电极包括基极和由基极承载的至少一个子电极。所述至少一个子电极的宽度小于所述基极的宽度，以赋予所述电流调平电极大致锥形，阶梯形或凸形的构造。

46. 发明申请

US20050155869A1 Electropolishing method for removing particles from wafer surface 有权
标题翻译：从晶片表面去除颗粒的电抛光方法
公开(公告)号：US20050155869A1
公开(公告)日：2005-07-21
申请号：US10761477
申请日：2004-01-20
申请人： Shih-Ho Lin , Chung-Chang Chen , Kei-Wei Chen , Shih-Tzung Chang , Chao-Lung Chen , Po-Jen Shih , Yu-Ku Lin , Ying-Lang Wang
发明人： Shih-Ho Lin , Chung-Chang Chen , Kei-Wei Chen , Shih-Tzung Chang , Chao-Lung Chen , Po-Jen Shih , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： B24B37/04 , C25D3/38 , C25D5/18 , C25D7/12 , C25F3/02 , H01L21/02 , H01L21/321 , H01L21/768 , B23H3/00
CPC分类号： H01L21/76843 , B24B37/042 , B24B37/046 , C25D3/38 , C25D5/18 , C25D7/123 , C25F3/02 , H01L21/02068 , H01L21/32115 , H01L21/76865 , H01L21/76873
摘要： An electropolishing method for removing potential device-contaminating particles from a wafer, is disclosed. The method includes immersing the wafer in an electropolishing electrolyte solution and removing defects and particles from the wafer by rotational friction between the wafer and the electrolyte solution in combination with electrolysis. The method is effective in removing particles from via openings of all sizes, including via openings having a width smaller than about 0.2 μm.
摘要翻译：公开了一种用于从晶片去除潜在的器件污染颗粒的电抛光方法。该方法包括将晶片浸入电解抛光电解质溶液中，并通过晶片和电解质溶液之间的旋转摩擦与电解结合从晶片去除缺陷和颗粒。该方法有效地从各种尺寸的通孔开口去除颗粒，包括宽度小于约0.2μm的通孔。

47. 发明授权

US06626741B2 Method for improving thickness uniformity on a semiconductor wafer during chemical mechanical polishing 有权
公开(公告)号：US06626741B2
公开(公告)日：2003-09-30
申请号：US09910633
申请日：2001-07-20
申请人： Ting-Chun Wang , Kei-Wei Chen , Shih-Tzung Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Ting-Chun Wang , Kei-Wei Chen , Shih-Tzung Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： B24B100
CPC分类号： B24B57/02 , B24B37/042
摘要： A method for improving thickness uniformity on a semiconductor wafer during a chemical mechanical polishing process capable of eliminating a wafer edge collapsing defect is described. In the method, slurry solution is removed from a peripheral edge portion of less than 10 mm wide on the surface of the polishing pad such that a concentration of the slurry can be effectively reduced in the peripheral region. The reduced slurry solution leads to a reduction in the removal rate on the wafer surface. The removal of slurry from the peripheral region can further be achieved by a mechanical means. A suitable width of the peripheral region of the polishing pad to be sprayed by an edge sprayer is less than 10 mm, and preferably between about 3 mm and about 5 mm. A suitable solvent to be sprayed is deionized water.

48. 发明授权

US09254548B2 Method of forming diamond conditioners for CMP process 有权
标题翻译：形成CMP工艺用金刚石调理剂的方法
公开(公告)号：US09254548B2
公开(公告)日：2016-02-09
申请号：US13455448
申请日：2012-04-25
申请人： Yen-Chang Chao , Kei-Wei Chen , Ying-Lang Wang
发明人： Yen-Chang Chao , Kei-Wei Chen , Ying-Lang Wang
IPC分类号： B24B53/017 , B24D3/06 , B24D3/28 , B24D18/00
CPC分类号： B24B53/12 , B24B53/017 , B24D3/06 , B24D3/28 , B24D18/00
摘要： A method for making a conditioner disk used in a chemical mechanical polishing (CMP) process comprises applying a first layer of at least one binder over a substrate; disposing a plurality of diamond particles on the first layer of the at least one first binder at the plurality of locations; and fixing the plurality of diamond particles to the substrate by heating the substrate to a raised temperature and then cooling the substrate. The plurality of diamond particles disposed over the substrate are configured to provide a working diamond ratio higher than 50% when the conditioner disk is used in a CMP process.
摘要翻译：用于制造在化学机械抛光（CMP）工艺中使用的调节盘的方法包括在衬底上施加至少一种粘合剂的第一层; 在所述多个位置处在所述至少一个第一粘合剂的所述第一层上设置多个金刚石颗粒; 以及通过将衬底加热到升高的温度然后冷却衬底，将多个金刚石颗粒固定到衬底上。设置在基板上的多个金刚石颗粒被配置为当在CMP工艺中使用调节盘时，提供高于50％的工作金刚石比例。

49. 发明授权

US08552529B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08552529B2
公开(公告)日：2013-10-08
申请号：US13488958
申请日：2012-06-05
申请人： Jung-Chih Tsao , Yu-Sheng Wang , Kei-Wei Chen , Ying-Lang Wang
发明人： Jung-Chih Tsao , Yu-Sheng Wang , Kei-Wei Chen , Ying-Lang Wang
IPC分类号： H01L21/02
CPC分类号： H01L27/0805 , H01L28/60 , H01L28/75
摘要： A semiconductor device is disclosed. The device includes a substrate; a first metal layer overlying the substrate; a dielectric layer overlying the first metal layer; and a second metal layer overlying the dielectric layer, wherein the first metal layer comprises: a first body-centered cubic lattice metal layer; a first underlayer, underlying the first body-centered cubic lattice metal layer, wherein the first underlayer is metal of body-centered cubic lattice and includes titanium (Ti), tungsten (W), molybdenum (Mo) or niobium (Nb); and a first interface of body-centered cubic lattice between the first body-centered cubic lattice metal layer and the first underlayer.
摘要翻译：公开了一种半导体器件。该装置包括基板; 覆盖衬底的第一金属层; 覆盖在第一金属层上的电介质层; 以及覆盖所述电介质层的第二金属层，其中所述第一金属层包括：第一体心立方晶格金属层; 第一底层，位于第一体心立方晶格金属层下面，其中第一底层是体心立方晶格的金属，包括钛（Ti），钨（W），钼（Mo）或铌（Nb）; 以及在第一体心立方晶格金属层和第一底层之间的体心立方晶格的第一界面。

50. 发明授权

US08551193B2 Nickel alloy target including a secondary metal 有权
标题翻译：镍合金靶包括二次金属
公开(公告)号：US08551193B2
公开(公告)日：2013-10-08
申请号：US13188182
申请日：2011-07-21
申请人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen
发明人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen
IPC分类号： C22C19/03 , H01L21/283
CPC分类号： H01L29/45 , C23C14/14 , C23C14/3414 , H01L21/28052 , H01L21/28518 , H01L21/2855 , H01L21/823418 , H01L29/456 , H01L29/665 , Y10T29/41
摘要： A target includes nickel and a secondary metal. The secondary metal has a volume percentage between about 1 percent and about 10 percent. The secondary metal has a density between about 5,000 kg/m3 and about 15,000 kg/m3.
摘要翻译：目标包括镍和二次金属。次级金属的体积百分比在约1％至约10％之间。二次金属具有约5,000kg / m 3至约15,000kg / m 3的密度。

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