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41. 发明授权

US09099444B2 3D integrated circuit package with through-mold first level interconnects 有权
标题翻译： 3D集成电路封装，具有通用模具一级互连
公开(公告)号：US09099444B2
公开(公告)日：2015-08-04
申请号：US13995778
申请日：2011-12-22
申请人： Debendra Mallik , Robert L. Sankman
发明人： Debendra Mallik , Robert L. Sankman
IPC分类号： H01L23/02 , H01L23/48 , H01L23/31 , H01L25/065 , H01L23/00 , H01L25/00 , H01L21/56
CPC分类号： H01L25/0657 , H01L21/56 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/82 , H01L23/3114 , H01L23/3135 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/051 , H01L2224/05147 , H01L2224/05541 , H01L2224/05571 , H01L2224/056 , H01L2224/05647 , H01L2224/12105 , H01L2224/13023 , H01L2224/131 , H01L2224/13111 , H01L2224/1403 , H01L2224/141 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/16265 , H01L2224/1703 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81203 , H01L2224/81986 , H01L2224/9202 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06568 , H01L2225/06582 , H01L2924/00014 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/1032 , H01L2924/12042 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1461 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/19043 , H01L2924/19103 , H01L2924/19104 , H01L2224/81 , H01L2924/00012 , H01L2924/014 , H01L2924/00 , H01L2224/05552 , H01L2924/01079 , H01L2224/11
摘要： 3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.
摘要翻译：描述了具有通过模具一级互连的3D集成电路封装以及形成这种封装的方法。例如，半导体封装包括衬底。底部半导体管芯具有表面积的活性侧。底部半导体管芯与主体侧远离衬底耦合到衬底。顶部半导体管芯具有活性侧，其表面积大于底部半导体管芯的表面积。顶部半导体管芯耦合到衬底，其中有源侧靠近衬底。底部半导体管芯的有源侧面向并导电耦合到顶部半导体管芯的有源侧。顶部半导体管芯通过旁路底部半导体管芯的一级互连导体耦合到衬底。

42. 发明申请

US20150171065A1 EMBEDDED MEMORY AND POWER MANAGEMENT SUBPACKAGE 有权
标题翻译：嵌入式存储器和电源管理单元
公开(公告)号：US20150171065A1
公开(公告)日：2015-06-18
申请号：US14104877
申请日：2013-12-12
申请人： John S. Guzek , Debendra Mallik , Sasha N. Oster , Timothy E. McIntosh
发明人： John S. Guzek , Debendra Mallik , Sasha N. Oster , Timothy E. McIntosh
IPC分类号： H01L25/18 , H01L23/48 , H01L21/56 , H01L23/00 , H01L25/00 , H01L23/31
CPC分类号： H01L25/18 , H01L23/3128 , H01L23/3675 , H01L23/481 , H01L23/49816 , H01L23/5384 , H01L23/5389 , H01L24/17 , H01L24/19 , H01L24/20 , H01L25/0652 , H01L25/50 , H01L2224/12105 , H01L2224/16145 , H01L2224/16225 , H01L2224/16235 , H01L2224/2518 , H01L2224/73253 , H01L2224/73259 , H01L2225/06513 , H01L2225/06517 , H01L2225/06548 , H01L2225/06562 , H01L2225/06589 , H01L2924/1205 , H01L2924/1206 , H01L2924/1427 , H01L2924/1432 , H01L2924/1434 , H01L2924/15321 , H01L2924/16251 , H01L2924/182
摘要： Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了允许诸如处理器和存储器的设备之间的相对短的连接的集成电路封装组件。在一个实施例中，封装组件包括嵌入到直接耦合到附接到子封装的另一管芯的子封装中的管芯。在一些实施例中，子包还可以包含电源管理装置。在一些实施例中，嵌入在子封装和/或功率管理器件中的管芯可以与耦合到子封装的管芯定义的区域重叠或位于其中，使得它们位于耦合到子封装的管芯和衬底之间子包。可以描述和/或要求保护其他实施例。

43. 发明授权

US09049807B2 Processes of making pad-less interconnect for electrical coreless substrate 有权
标题翻译：制造无电芯基板的无焊接互连的工艺
公开(公告)号：US09049807B2
公开(公告)日：2015-06-02
申请号：US12215018
申请日：2008-06-24
申请人： Javier Soto , Charan Gurumurthy , Robert Nickerson , Debendra Mallik
发明人： Javier Soto , Charan Gurumurthy , Robert Nickerson , Debendra Mallik
IPC分类号： H05K3/36 , H05K3/40 , H01L21/48 , H01L23/498 , H05K3/46 , H01L23/31 , H05K1/11 , H05K3/00 , H05K3/20 , H05K3/24 , H05K3/28 , H05K3/34
CPC分类号： H01L24/17 , H01L21/4857 , H01L21/486 , H01L23/3128 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L2224/05571 , H01L2224/05573 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2924/00014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/2064 , H01L2924/20642 , H01L2924/20643 , H01L2924/20644 , H05K1/113 , H05K3/0035 , H05K3/007 , H05K3/20 , H05K3/244 , H05K3/28 , H05K3/3457 , H05K3/4007 , H05K3/4682 , H05K2201/0367 , H05K2201/096 , H05K2203/0152 , H05K2203/1536 , Y10T29/49147 , H01L2924/00 , H01L2224/05599
摘要： A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.
摘要翻译：微电子器件包括层叠安装基板，其包括裸片侧和具有设置在安装基板裸片侧的凹部中的表面光洁度层的平台侧。导电的第一插头与表面光洁度层接触，并且导电的后续插头设置在安装衬底接地侧上，并且其电耦合到导电的第一插头并且直接设置在导电的第一插头的正下方。

44. 发明授权

US08901748B2 Direct external interconnect for embedded interconnect bridge package 有权
标题翻译：直接外部互连用于嵌入式互连桥式封装
公开(公告)号：US08901748B2
公开(公告)日：2014-12-02
申请号：US13828947
申请日：2013-03-14
申请人： Mathew J. Manusharow , Debendra Mallik
发明人： Mathew J. Manusharow , Debendra Mallik
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/34 , H01L23/02 , H01L23/58 , H01L23/498 , H01L23/00
CPC分类号： H01L24/82 , H01L23/36 , H01L23/5383 , H01L23/5385 , H01L23/5386 , H01L24/20 , H01L25/0655 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/16148 , H01L2224/16238 , H01L2224/73267 , H01L2924/12042 , H01L2924/014 , H01L2924/00
摘要： An external direct connection usable for an embedded interconnect bridge package is described. In one example, a package has a substrate, a first semiconductor die having a first bridge interconnect region, and a second semiconductor die having a second bridge interconnect region. The package has a bridge embedded in the substrate, the bridge having a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region, and an external connection rail extending between the interconnect bridge and the first and second semiconductor dies to supply external connection to the first and second bridge interconnect regions.
摘要翻译：描述可用于嵌入式互连桥式封装的外部直接连接。在一个示例中，封装具有基板，具有第一桥接互连区域的第一半导体管芯和具有第二桥接互连区域的第二半导体管芯。所述封装具有嵌入在所述基板中的桥，所述桥具有用于连接到所述第一桥互连区域的第一接触区域和用于连接到所述第二桥接互连区域的第二接触区域，以及在所述互连桥和所述第一和第二半导体管芯提供到所述第一和第二桥互连区域的外部连接。

45. 发明申请

US20140264791A1 DIRECT EXTERNAL INTERCONNECT FOR EMBEDDED INTERCONNECT BRIDGE PACKAGE 有权
标题翻译：嵌入式互连桥封装的直接外部互连
公开(公告)号：US20140264791A1
公开(公告)日：2014-09-18
申请号：US13828947
申请日：2013-03-14
申请人： MATHEW J. MANUSHAROW , Debendra Mallik
发明人： MATHEW J. MANUSHAROW , Debendra Mallik
IPC分类号： H01L23/498 , H01L23/00
CPC分类号： H01L24/82 , H01L23/36 , H01L23/5383 , H01L23/5385 , H01L23/5386 , H01L24/20 , H01L25/0655 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/16148 , H01L2224/16238 , H01L2224/73267 , H01L2924/12042 , H01L2924/014 , H01L2924/00
摘要： An external direct connection usable for an embedded interconnect bridge package is described. In one example, a package has a substrate, a first semiconductor die having a first bridge interconnect region, and a second semiconductor die having a second bridge interconnect region. The package has a bridge embedded in the substrate, the bridge having a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region, and an external connection rail extending between the interconnect bridge and the first and second semiconductor dies to supply external connection to the first and second bridge interconnect regions.
摘要翻译：描述可用于嵌入式互连桥式封装的外部直接连接。在一个示例中，封装具有基板，具有第一桥接互连区域的第一半导体管芯和具有第二桥接互连区域的第二半导体管芯。所述封装具有嵌入在所述基板中的桥，所述桥具有用于连接到所述第一桥互连区域的第一接触区域和用于连接到所述第二桥接互连区域的第二接触区域，以及在所述互连桥和所述第一和第二半导体管芯提供到所述第一和第二桥互连区域的外部连接。

46. 发明授权

US08617990B2 Reduced PTH pad for enabling core routing and substrate layer count reduction 有权
公开(公告)号：US08617990B2
公开(公告)日：2013-12-31
申请号：US12973596
申请日：2010-12-20
申请人： Debendra Mallik , Mihir K. Roy
发明人： Debendra Mallik , Mihir K. Roy
IPC分类号： H01L21/44
CPC分类号： H01L23/49827 , H01L21/4857 , H01L23/49822 , H01L23/49838 , H01L23/49894 , H01L2224/16225 , H05K1/113 , H05K1/115
摘要： Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.

47. 发明授权

US07794236B2 Land grid array (LGA) socket for various package sizes 有权
标题翻译：用于各种封装尺寸的栅格阵列（LGA）插座
公开(公告)号：US07794236B2
公开(公告)日：2010-09-14
申请号：US12335353
申请日：2008-12-15
申请人： Debendra Mallik , Brent Stone
发明人： Debendra Mallik , Brent Stone
IPC分类号： H01R12/00
CPC分类号： H05K7/1053 , Y10T29/49204
摘要： An LGA socket for receiving substrate packages of various sizes and a method of fabricating the socket. In an embodiment, the socket has a planar surface for seating a substrate package. Socket contacts are disposed on the planar surface in a layout common to the layout of interconnects formed on the bottom of substrate packages the socket is designed to receive. A plurality of socket locating features is formed on the socket body to prevent lateral displacement of a reference substrate package. A corresponding number of package locating features are formed on the substrate body of packages larger than the reference substrate package. Each of the socket locating features meshes with the corresponding package locating feature of the larger package.
摘要翻译：用于接收各种尺寸的衬底封装的LGA插座和制造插座的方法。在一个实施例中，插座具有用于安置衬底封装的平坦表面。插座触点以与形成在插座被设计为接收的衬底封装的底部上的互连布局相同的布局布置在平面表面上。多个插座定位特征形成在插座主体上，以防止参考基板封装的横向位移。在大于参考基板封装的封装的基板主体上形成相应数量的封装定位特征。每个插座定位功能都与较大包装的相应包装定位功能相啮合。

48. 发明申请

US20100151706A1 Land Grid Array (LGA) Socket for Various Package Sizes 有权
标题翻译：用于各种封装尺寸的栅格阵列（LGA）插座
公开(公告)号：US20100151706A1
公开(公告)日：2010-06-17
申请号：US12335353
申请日：2008-12-15
申请人： Debendra Mallik , Brent Stone
发明人： Debendra Mallik , Brent Stone
IPC分类号： H01R12/00 , H01R43/00
CPC分类号： H05K7/1053 , Y10T29/49204
摘要： An LGA socket for receiving substrate packages of various sizes and a method of fabricating the socket. In an embodiment, the socket has a planar surface for seating a substrate package. Socket contacts are disposed on the planar surface in a layout common to the layout of interconnects formed on the bottom of substrate packages the socket is designed to receive. A plurality of socket locating features is formed on the socket body to prevent lateral displacement of a reference substrate package. A corresponding number of package locating features are formed on the substrate body of packages larger than the reference substrate package. Each of the socket locating features meshes with the corresponding package locating feature of the larger package.
摘要翻译：用于接收各种尺寸的衬底封装的LGA插座和制造插座的方法。在一个实施例中，插座具有用于安置衬底封装的平坦表面。插座触点以与形成在插座被设计为接收的衬底封装的底部上的互连布局相同的布局布置在平面表面上。多个插座定位特征形成在插座主体上以防止参考基板封装的横向位移。在大于参考基板封装的封装的基板主体上形成相应数量的封装定位特征。每个插座定位功能都与较大包装的相应包装定位功能相啮合。

49. 发明授权

US07517787B2 C4 joint reliability 有权
标题翻译： C4联合可靠性
公开(公告)号：US07517787B2
公开(公告)日：2009-04-14
申请号：US11087180
申请日：2005-03-22
申请人： Sairam Agraharam , Carlton Hanna , Dongming He , Vasudeva Atluri , Debendra Mallik , Matthew Escobido , Sujit Sharan
发明人： Sairam Agraharam , Carlton Hanna , Dongming He , Vasudeva Atluri , Debendra Mallik , Matthew Escobido , Sujit Sharan
IPC分类号： H01L23/48
CPC分类号： H01L24/13 , H01L24/11 , H01L24/16 , H01L2224/05001 , H01L2224/05026 , H01L2224/05568 , H01L2224/05655 , H01L2224/13 , H01L2224/13017 , H01L2224/13099 , H01L2224/16058 , H01L2924/00014 , H01L2924/01006 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/00 , H01L2224/05099
摘要： In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.
摘要翻译：在一个实施例中，本发明提供了一种方法，其包括在管芯上制造管芯凸块，所述管芯凸块的形状和尺寸被设计成至少减小所使用的焊料材料的流动，以将管芯凸块附接到封装衬底位于模具凸块下方的冶金（UBM）层。有利地，该方法可以包括执行衬底回流操作以将封装衬底附接到管芯凸块，而不执行单独的晶片回流操作以回流管芯凸块。

50. 发明授权

US07321172B2 Selective plating of package terminals 有权
标题翻译：包装端子的选择性电镀
公开(公告)号：US07321172B2
公开(公告)日：2008-01-22
申请号：US11227532
申请日：2005-09-14
申请人： Dustin P. Wood , Debendra Mallik
发明人： Dustin P. Wood , Debendra Mallik
IPC分类号： H01L23/48
CPC分类号： H01L23/498 , H01L21/4846 , H01L2224/16225 , H01L2924/3011 , H05K3/242 , H05K3/243 , H05K2201/0391 , H05K2201/094 , H05K2203/072 , H05K2203/0723 , H05K2203/073
摘要： In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.
摘要翻译：在一个实施例中，公开了一种包括提供具有第一焊盘和第二焊盘的半导体焊盘封装的方法。使用第一工艺将包含第一金属的第一层沉积在第一焊盘上。然后使用第二工艺将第二金属沉积在第一焊盘和第一层上。在另一个实施例中，第一工艺包括电镀工艺，第二工艺包括直接浸金（DIG）工艺。在另一实施例中，第一焊盘是电源或接地焊盘，第二焊盘是信号焊盘。

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