专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20130190482A1 METHOD FOR ONE-STEP PURIFICATION OF RECOMBINANT HELICOBACTER PYLORI NEUTROPHIL-ACTIVATING PROTEIN 有权
标题翻译：重组纯化乙酰胆碱激活蛋白一步纯化方法
公开(公告)号：US20130190482A1
公开(公告)日：2013-07-25
申请号：US13560593
申请日：2012-07-27
申请人： Hua-Wen Fu , Kuo-Shun Shih , Chih-Chang Lin , Yu-Chi Yang
发明人： Hua-Wen Fu , Kuo-Shun Shih , Chih-Chang Lin , Yu-Chi Yang
IPC分类号： C07K1/22
CPC分类号： C07K14/205
摘要： Helicobacter pylori is closely associated with chronic gastritis, peptic ulcer disease, and gastric adenocarcinoma. Helicobacter pylori neutrophil-activating protein (HP-NAP), a virulence factor of Helicobacter pylori, plays an important role in pathogenesis of Helicobacter pylori infection. Since HP-NAP has been proposed as a candidate vaccine against Helicobacter pylori infection, an efficient way to obtain pure HP-NAP needs to be developed. In the present invention, recombinant HP-NAP expressed in Bacillus subtilis and Escherichia coli was purified through a single step of DEAE Sephadex ion-exchange chromatography with high purity. Also, purified recombinant HP-NAP was able to stimulate neutrophils to produce reactive oxygen species. Thus, recombinant HP-NAP obtained from our Bacillus subtilis expression system and Escherichia coli expression system is functionally active. Furthermore, this one-step negative purification method should provide an efficient way to purify recombinant HP-NAP expressed in Bacillus subtilis and Escherichia coli for basic studies, vaccine development, or drug design.
摘要翻译：幽门螺杆菌与慢性胃炎，消化性溃疡病和胃腺癌密切相关。幽门螺杆菌嗜中性粒细胞激活蛋白（HP-NAP）是幽门螺杆菌的毒力因子，在幽门螺杆菌感染的发病机制中起重要作用。由于HP-NAP已被提出作为针对幽门螺杆菌感染的候选疫苗，因此需要开发获得纯HP-NAP的有效途径。在本发明中，通过单纯DEAE Sephadex离子交换层析纯化纯化在枯草芽孢杆菌和大肠杆菌中表达的重组HP-NAP。此外，纯化的重组HP-NAP能够刺激嗜中性粒细胞产生活性氧。因此，从我们的枯草芽孢杆菌表达系统和大肠杆菌表达系统获得的重组HP-NAP在功能上是活性的。此外，该一步负纯化方法应提供一种有效的方法来纯化在枯草芽孢杆菌和大肠杆菌中表达的重组HP-NAP用于基础研究，疫苗开发或药物设计。

42. 发明授权

US08493124B2 Low minimum power supply voltage level shifter 有权
标题翻译：低最小电源电压电平转换器
公开(公告)号：US08493124B2
公开(公告)日：2013-07-23
申请号：US12843479
申请日：2010-07-26
申请人： Chan-Hong Chern , Fu-Lung Hsueh , Ming-Chieh Huang , Chih-Chang Lin
发明人： Chan-Hong Chern , Fu-Lung Hsueh , Ming-Chieh Huang , Chih-Chang Lin
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： A level shifter includes one PMOS and two NMOS transistors. A source of the first NMOS transistor is coupled to a low power supply voltage. An input signal is coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor. The input signal has a voltage level up to a first power supply voltage. A source of the PMOS transistor is coupled to a second power supply voltage, higher than the first power supply voltage. An output signal is coupled between the PMOS and the first NMOS transistors. The first NMOS transistor is arranged to pull down the output signal when the input signal is a logical 1, and the second NMOS transistor is arranged to enable the PMOS transistor to pull up the output signal to a logical 1 at the second power supply voltage when the input signal is a logical 0.
摘要翻译：电平移位器包括一个PMOS和两个NMOS晶体管。第一NMOS晶体管的源极耦合到低电源电压。输入信号耦合到第一NMOS晶体管的栅极和第二NMOS晶体管的源极。输入信号具有高达第一电源电压的电压电平。 PMOS晶体管的源极耦合到高于第一电源电压的第二电源电压。输出信号耦合在PMOS和第一NMOS晶体管之间。第一NMOS晶体管被布置为当输入信号为逻辑1时下拉输出信号，并且第二NMOS晶体管被布置为使得PMOS晶体管能够以第二电源电压将输出信号上拉至逻辑1，输入信号为逻辑0。

43. 发明授权

US08436671B2 Level shifters having diode-connected devices for input-output interfaces 有权
标题翻译：电平移位器具有用于输入 - 输出接口的二极管连接器件
公开(公告)号：US08436671B2
公开(公告)日：2013-05-07
申请号：US12859456
申请日：2010-08-19
申请人： Chan-Hong Chern , Fu-Lung Hsueh , Chih-Chang Lin , Yuwen Swei , Ming-Chieh Huang
发明人： Chan-Hong Chern , Fu-Lung Hsueh , Chih-Chang Lin , Yuwen Swei , Ming-Chieh Huang
IPC分类号： H03L5/00
CPC分类号： H03K3/02 , H03K19/018521 , H03K19/018528
摘要： A level shifter includes an input node, an output node, a pull-up transistor, a pull-down transistor, and at least one diode-connected device coupled between the pull-up transistor and the pull-down transistor. The level shifter is arranged to be coupled to a high power supply voltage, to receive an input signal having a first voltage level at the input node, and to supply an output signal having a second voltage level at the output node. The high power supply voltage is higher than the first voltage level. The at least one diode-connected device allows the output signal to be pulled up to about a first diode voltage drop below the high power supply voltage and/or to be pulled down to about a second diode voltage drop above ground. The first diode voltage drop and the second diode voltage drop are from the at least one diode-connected device.
摘要翻译：电平移位器包括输入节点，输出节点，上拉晶体管，下拉晶体管以及耦合在上拉晶体管和下拉晶体管之间的至少一个二极管连接器件。电平移位器被布置为耦合到高电源电压，以在输入节点处接收具有第一电压电平的输入信号，并且在输出节点处提供具有第二电压电平的输出信号。高电源电压高于第一电压电平。所述至少一个二极管连接的装置允许输出信号被上拉到大约低于高电源电压的第一二极管电压降和/或被下拉到大约地面上的第二二极管电压降。第一二极管电压降和第二二极管压降来自至少一个二极管连接的器件。

44. 发明申请

US20110285445A1 DRIVE LOOP FOR MEMS OSCILLATOR 有权
标题翻译：用于MEMS振荡器的驱动环
公开(公告)号：US20110285445A1
公开(公告)日：2011-11-24
申请号：US12782064
申请日：2010-05-18
申请人： Ming-Chieh Huang , Chiang Pu , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei
发明人： Ming-Chieh Huang , Chiang Pu , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei
IPC分类号： H03L5/00 , H03B5/30 , H02K33/00
CPC分类号： H03B5/30
摘要： Some embodiments regard a method comprising: generating a current according to a movement of the MEMS device; the movement is controlled by a control signal; generating a peak voltage according to the current; and adjusting the control signal when the peak voltage is out of a predetermined range.
摘要翻译：一些实施例涉及一种方法，包括：根据MEMS装置的移动产生电流; 移动由控制信号控制; 根据电流产生峰值电压; 以及当峰值电压超出预定范围时调节控制信号。

45. 发明申请

US20080127015A1 Method and system for verifying power specifications of a low power design 有权
标题翻译：用于验证低功率设计功率规格的方法和系统
公开(公告)号：US20080127015A1
公开(公告)日：2008-05-29
申请号：US11590076
申请日：2006-10-30
申请人： Bharat Chandramouli , Huan-Chih Tsai , Manish Pandey , Chih-Chang Lin , Madan M. Das
发明人： Bharat Chandramouli , Huan-Chih Tsai , Manish Pandey , Chih-Chang Lin , Madan M. Das
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： Method and system for verifying power specifications of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of the low power design, receiving a power specification file for describing power requirements of the low power design and verifying the power specification file in accordance with the RTL netlist representation of the low power design. The method further includes verifying completeness, compatibility, and consistency of power requirements for the low power design.
摘要翻译：公开了用于验证低功率设计的功率规格的方法和系统。该方法包括接收低功率设计的寄存器传送级（RTL）网表表示，接收用于描述低功率设计的功率需求的功率规格文件，并根据低功率设计的RTL网表表示验证功率规格文件电源设计。该方法还包括验证低功率设计的功率要求的完整性，兼容性和一致性。

46. 发明授权

US07137084B1 Similarity-driven synthesis for equivalence checking of complex designs 有权
标题翻译：相似性驱动的复杂设计等价检验综合
公开(公告)号：US07137084B1
公开(公告)日：2006-11-14
申请号：US10832771
申请日：2004-04-26
申请人： Kuang-Chien Chen , Chih-Chang Lin , Cheng-Ta Hsieh , Yifeng Wang
发明人： Kuang-Chien Chen , Chih-Chang Lin , Cheng-Ta Hsieh , Yifeng Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method for modeling a circuit design includes synthesizing the circuit design to create a first gate-level representation of the circuit design. The method also includes analyzing a second gate-level representation of the circuit design to learn architecture information, and resynthesizing the first gate-level representation of the circuit design to incorporate the learned architecture information from the second gate-level representation of the circuit design. A computer-readable storage medium has stored thereon computer instructions that, when executed by a computer, cause the computer to synthesize a circuit design to create a first gate-level representation of the circuit design. The computer instructions also cause the computer to analyze a second gate-level representation of the circuit design to learn architecture information, and resynthesize the first gate-level representation of the circuit design to incorporate the learned architecture information from the second gate-level representation of the circuit design.
摘要翻译：用于对电路设计进行建模的方法包括合成电路设计以创建电路设计的第一门级表示。该方法还包括分析电路设计的第二门级表示以学习架构信息，以及重新合成电路设计的第一门级表示，以从电路设计的第二门级表示中并入所学习的体系结构信息。计算机可读存储介质上存储有计算机指令，其在由计算机执行时使计算机合成电路设计以创建电路设计的第一门级表示。计算机指令还使得计算机分析电路设计的第二门级表示以学习架构信息，并重新合成电路设计的第一门级表示，以将来自第二门级表示的学习架构信息电路设计。

47. 发明授权

US07057672B2 Method and apparatus for high frequency data transmission and testability in a low voltage, differential swing design 失效
公开(公告)号：US07057672B2
公开(公告)日：2006-06-06
申请号：US09823078
申请日：2001-03-29
申请人： Bal S. Sandhu , Yanmei Tian , Chih-Chang Lin
发明人： Bal S. Sandhu , Yanmei Tian , Chih-Chang Lin
IPC分类号： H04N5/38 , H03F3/45
CPC分类号： G09G5/006 , G09G5/363 , G09G2330/12
摘要： A high frequency data transmission circuit including design for testability (DFT) features. An integrated circuit includes core control logic to provide a data signal and output drive logic including a local data latch and a transmitter. The data latch receives the data signal and provides true and complementary forms of the data signal to the transmitter over symmetrical signal paths. The transmitter provides an output signal to an external receiver.

48. 发明申请

US20050146245A1 Ceramic transformer level driving circuit 失效
标题翻译：陶瓷变压器电平驱动电路
公开(公告)号：US20050146245A1
公开(公告)日：2005-07-07
申请号：US10745592
申请日：2003-12-29
申请人： Chin-Wen Chou , Eddie Cheng , K. Wu , Chih-Chang Lin
发明人： Chin-Wen Chou , Eddie Cheng , K. Wu , Chih-Chang Lin
IPC分类号： H01L41/04 , H01L41/107 , H02M7/217 , H05B41/282
CPC分类号： H05B41/2828 , H01L41/044
摘要： A ceramic transformer level driving circuit mainly aims to transform a low voltage signal to another low voltage signal through an amplified signal to drive a medium voltage system. It includes a control unit to generate a resonant frequency and output phase signal waveforms, a waveform transformation unit to provide phase signals and perform waveform phase transformation for the phase signal waveforms, and a medium voltage driving circuit which includes a floating level unit and a driving unit which receives a medium voltage electric input. The driving unit actuates opening and closing at different time to enable the floating level unit to output a voltage floating level thereby to drive a ceramic transformer to control the medium voltage system through a low voltage level.
摘要翻译：陶瓷变压器电平驱动电路主要是通过放大信号将低电压信号转换为另一低电压信号，以驱动中压系统。它包括产生谐振频率和输出相位信号波形的控制单元，提供相位信号并对相位信号波形执行波形相位变换的波形变换单元，以及包括浮置电平单元和驱动的中压驱动电路接收中压电输入的单元。驱动单元在不同时间启动打开和关闭，以使浮动水平单元能够输出电压浮动电平，从而驱动陶瓷变压器以通过低电压电平控制中压系统。

49. 发明申请

US20170061447A1 MARKETING SYSTEM OF COLLECTING AND EXCHANGING POINT 审中-公开
标题翻译：收集和交换点营销系统
公开(公告)号：US20170061447A1
公开(公告)日：2017-03-02
申请号：US14836962
申请日：2015-08-27
申请人： Fu-Kuang Wang , Hsiang-Chun Tseng , Li-Hua Huang , Chih-Chang Lin , Chin-Yu Chen
发明人： Fu-Kuang Wang , Chih-Chang Lin
IPC分类号： G06Q30/02
CPC分类号： G06Q30/0201
摘要： A marketing system of collecting and exchanging point includes a server side device, a plurality of shop side devices, and a plurality of consumption side devices. The server side device stores shop accounts, information of collecting and exchanging point, customer accounts, and customer point information. Each shop side device is respectively corresponding to one shop account. Each consumption side device is respectively corresponding to one customer account. Each consumption side device respectively has a point collecting module and a point exchanging module for executing a point collecting action and a point exchanging action. The server side device gathers and computes exchangeable points being collected and exchanged with regard to a plurality of the shop accounts. The exchangeable points of the customer account are divided into a plurality of exchangeable points specialized for each of the shop accounts.
摘要翻译：收集交易点的营销系统包括服务器侧设备，多个店面设备和多个消费侧设备。服务器端设备存储店铺帐号，收集和交换点的信息，客户账户和客户点信息。每个店铺设备分别对应于一个店铺帐户。每个消费侧设备分别对应于一个客户帐户。每个消费侧设备分别具有点收集模块和用于执行点收集动作和点交换动作的点交换模块。服务器端设备收集并计算关于多个店铺帐户的可交换点的收集和交换。客户帐户的可交换点被分为专门用于每个商店帐户的多个可交换点。

50. 发明授权

US08884665B2 Multiple-phase clock generator 有权
标题翻译：多相时钟发生器
公开(公告)号：US08884665B2
公开(公告)日：2014-11-11
申请号：US13084817
申请日：2011-04-12
申请人： Chih-Chang Lin , Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung
发明人： Chih-Chang Lin , Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung
IPC分类号： H03B19/00 , H03K5/15
CPC分类号： H03K5/15013
摘要： A multiple-phase clock generator includes at least one stage of dividers. A clock signal is supplied as a first stage clock input to dividers in a first stage of dividers. An N-th stage includes 2N dividers, where N is a positive integer number. Each divider in the first stage is configured to divide a first clock frequency of the first stage clock input by 2 to provide a first stage output. Each divider in the N-th stage is configured to divide an N-th clock frequency of an N-th stage clock input by 2 to provide an N-th stage output. The N-th stage outputs from the dividers in the N-th stage provide 2N-phase clock signals that are equally distributed with a same phase difference between adjacent phase clock signals.
摘要翻译：多相时钟发生器包括至少一个分频器级。时钟信号作为第一级时钟输入提供给分频器的第一级中的分频器。第N级包括2N个分频器，其中N是正整数。第一级中的每个分频器被配置为将第一级时钟输入的第一时钟频率除以2以提供第一级输出。第N级中的每个除法器被配置为将输入的第N级时钟的第N个时钟频率除以2以提供第N级输出。在第N级的分频器的第N级输出提供2N相位时钟信号，它们在相邻的相位时钟信号之间以相同的相位差均匀分布。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式