专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US4994688A Semiconductor device having a reference voltage generating circuit 失效
标题翻译：具有基准电压发生电路的半导体装置
公开(公告)号：US4994688A
公开(公告)日：1991-02-19
申请号：US323966
申请日：1989-03-15
申请人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
发明人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
IPC分类号： G05F1/46 , G05F3/24 , G11C5/14 , G11C11/4074 , H01L27/02
CPC分类号： G11C5/147 , G05F1/465 , G05F3/245 , G05F3/247 , G11C11/4074 , H01L27/0203 , Y10S323/907
摘要： Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16 M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.
摘要翻译：涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。提供了改进的测试这些电路的方法。

42. 发明授权

US4942555A Bi-MOS semiconductor memory having high soft error immunity 失效
标题翻译：具有高软误差抗扰度的Bi-MOS半导体存储器
公开(公告)号：US4942555A
公开(公告)日：1990-07-17
申请号：US376865
申请日：1989-07-07
申请人： Hisayuki Higuchi , Makoto Suzuki , Noriyuki Homma , Kiyoo Itoh
发明人： Hisayuki Higuchi , Makoto Suzuki , Noriyuki Homma , Kiyoo Itoh
IPC分类号： G11C11/418 , G11C11/419
CPC分类号： G11C11/418 , G11C11/419
摘要： A semiconductor memory is provided having high reliability, and which particularly prevents data destruction by rays, and the like. In a semiconductor memory for detecting memory data from the conduction ratio between a transistor of a flip-flop type memory cell connected to selected word line and data line pairs and a load device of the data line, an arrangement is provided for setting the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of a data transfer MOS transistor of the memory cell. The signal read out from the memory cell is then applied through the data line to a differential amplifier using the base or gate of a junction type transistor as its input. Particularly to set the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of the data transfer MOS transistor of the memory cell, a device having high driving capability such as a bipolar transistor is used as the load of the data line. The word line voltage is changed over to two stages so that the data line voltage V.sub.D and the word line voltage V.sub.W satisfy the relation V.sub.W V.sub.D +V.sub.TH in a write cycle (where V.sub.TH is the threshold voltage of NMOS inside the memory cell).
摘要翻译：提供了具有高可靠性的半导体存储器，并且特别地防止了由于光线的数据破坏等。在用于根据连接到所选字线的触发器型存储单元的晶体管与数据线对之间的导通率以及数据线的负载装置的导通比来检测存储器数据的半导体存储器中，提供了用于设置字线电压低于数据线电压和存储单元的数据传输MOS晶体管的阈值电压之和的电压。从存储单元读出的信号然后通过数据线施加到使用结型晶体管的基极或栅极作为其输入的差分放大器。特别是为了将字线电压设定为低于数据线电压和存储单元的数据传输MOS晶体管的阈值电压之和的电压，使用诸如双极型晶体管的具有高驱动能力的器件作为负载的数据线。字线电压转换为两级，使得数据线电压VD和字线电压VW在读周期中满足关系VW VD + VTH（其中VTH 是存储单元内的NMOS的阈值电压）。

43. 发明授权

US4825418A Semiconductor memory 失效
公开(公告)号：US4825418A
公开(公告)日：1989-04-25
申请号：US171772
申请日：1988-03-22
申请人： Kiyoo Itoh , Ryoichi Hori
发明人： Kiyoo Itoh , Ryoichi Hori
IPC分类号： G11C11/413 , G11C5/06 , G11C11/401 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C11/40 , G11C13/00
CPC分类号： G11C11/4096 , G11C11/4087 , G11C11/4097 , G11C5/06 , G11C5/063
摘要： A semiconductor memory having a structure wherein each of data lines intersecting word lines is divided into a plurality of sub lines in its lengthwise direction, memory cells are arranged at the points of intersection between the divided sub lines and the word lines, common input/output lines are disposed in common to a plurality of such sub lines, the common input/output lines and the plurality of sub lines are respectively connected by switching elements, and the switching elements are connected to a decoder through control lines and are selectively driven by control signals generated from the decorder.

44. 发明授权

US4748591A Semiconductor memory 失效
公开(公告)号：US4748591A
公开(公告)日：1988-05-31
申请号：US38370
申请日：1987-04-14
申请人： Kiyoo Itoh , Ryoichi Hori
发明人： Kiyoo Itoh , Ryoichi Hori
IPC分类号： G11C11/413 , G11C5/06 , G11C11/401 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C11/40
CPC分类号： G11C11/4096 , G11C11/4087 , G11C11/4097 , G11C5/06 , G11C5/063
摘要： A semiconductor memory having a structure wherein each of data lines intersecting word lines is divided into a plurality of sub lines in its lengthwise direction, memory cells are arranged at the points of intersection between the divided sub lines and the word lines, common input/output lines are disposed in common to a plurality of such sub lines, the common input/output lines and the plurality of sub lines are respectively connected by switching elements, and the switching elements are connected to a decoder through control lines and are selectively driven by control signals generated from the decoder.

45. 发明授权

US4482985A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US4482985A
公开(公告)日：1984-11-13
申请号：US368162
申请日：1982-04-14
申请人： Kiyoo Itoh , Ryoichi Hori
发明人： Kiyoo Itoh , Ryoichi Hori
IPC分类号： G05F1/46 , G11C5/14 , G11C11/4074 , H01L27/02 , G11C7/00
CPC分类号： H01L27/0218 , G05F1/465 , G11C11/4074 , G11C5/145 , G11C5/147
摘要： In order to permit reduced component size without reduction of an external power supply voltage, a semiconductor integrated circuit includes at least three circuits. The first of these three circuits converts the external power source voltage to an internal power source voltage which is smaller than the external power voltage. A second circuit is supplied with the external power source voltage and is responsive to first signals which regulate an operation of the integrated circuit. This second circuit generates second signals which control the integrated circuit so that the integrated circuit performs the desired regulated operation. To carry this out, the second circuit includes at least first transistors which are supplied with the external power source voltage and responsive to the first signals. The second signals generated by the second circuit have amplitudes smaller than those of the first signals. The third circuit is supplied with the internal power source voltage and responsive to the second signals provided by the second circuit to perform the regulated operation. This third circuit includes at least second transistors which are supplied with the internal power source voltage and which have a smaller size than that of the first transistors. Thus, by virtue of this arrangement, the third circuit can carry out the desired regulated operation of the semiconductor integrated circuit using smaller elements and a lower voltage without the need for reducing the external power supply voltage level.
摘要翻译：为了在不降低外部电源电压的前提下减小组件尺寸，半导体集成电路至少包括三个电路。这三个电路中的第一个将外部电源电压转换为小于外部电源电压的内部电源电压。第二电路被提供有外部电源电压，并响应于调节集成电路的操作的第一信号。该第二电路产生控制集成电路的第二信号，使得集成电路执行期望的调节操作。为了实现这一点，第二电路至少包括第一晶体管，其被提供有外部电源电压并响应于第一信号。由第二电路产生的第二信号的幅度小于第一信号的幅度。第三电路被提供有内部电源电压并且响应于由第二电路提供的第二信号来执行调节操作。该第三电路至少包括第二晶体管，其被提供有内部电源电压并且具有比第一晶体管小的尺寸。因此，通过这种布置，第三电路可以使用更小的元件和更低的电压来执行半导体集成电路的期望的调节操作，而不需要降低外部电源电压电平。

46. 发明授权

US4316265A Memory device with high speed memory cell selection mechanism 失效
标题翻译：具有高速存储单元选择机制的存储器件
公开(公告)号：US4316265A
公开(公告)日：1982-02-16
申请号：US94927
申请日：1979-11-16
申请人： Hirotoshi Tanaka , Yoshiki Kawajiri , Kouetsu Chiba , Ryoichi Hori , Kiyoo Itoh
发明人： Hirotoshi Tanaka , Yoshiki Kawajiri , Kouetsu Chiba , Ryoichi Hori , Kiyoo Itoh
IPC分类号： G11C11/413 , G11C8/00 , G11C11/408 , G11C11/40
CPC分类号： G11C11/4087 , G11C8/00
摘要： In a memory device, row and column decoders are connected through a common address signal line to an address buffer, and the row decoder is connected through a switch to the common address signal line. When the address buffer delivers a first address signal, the switch is turned on so that the first address signal is applied to both of the column and row decoders. The column decoder includes therein provision for disabling the column decoder when the first address signal is applied to column decoder. The column decoder therefore does not respond to the first address signal. Subsequently, when the address buffer delivers a second address signal, the switch is turned off so that the row decoder is not applied with the second address signal but the column decoder responds to the second address signal. Thus, the row and column address respond to the first and second address signals respectively.
摘要翻译：在存储器件中，行和列解码器通过公共地址信号线连接到地址缓冲器，并且行解码器通过开关连接到公共地址信号线。当地址缓冲器传送第一个地址信号时，开关导通，使得第一个地址信号被应用于列和行解码器。列解码器包括其中当第一地址信号被应用于列解码器时禁用列解码器的设置。因此，列解码器不响应于第一地址信号。随后，当地址缓冲器传送第二地址信号时，开关被关断，使得行解码器不被施加第二地址信号，但是列译码器响应于第二地址信号。因此，行和列地址分别响应于第一和第二地址信号。

47. 发明授权

US08035147B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08035147B2
公开(公告)日：2011-10-11
申请号：US12768514
申请日：2010-04-27
申请人： Kiyoo Itoh , Riichiro Takemura
发明人： Kiyoo Itoh , Riichiro Takemura
IPC分类号： H01L27/108
CPC分类号： H01L27/10897 , G11C11/4091 , G11C11/4097 , G11C2211/4016 , H01L27/0207 , H01L27/108 , H01L27/1203 , H01L27/1207
摘要： A high-speed and low-voltage DRAM memory cell capable of operating at 1 V or less and an array peripheral circuit are provided. A DRAM cell is comprised of a memory cell transistor and planar capacitor which utilize a FD-SOI MOST structure. Since there is no junction leakage current, loss of stored charge is eliminated, and the low-voltage operation can be realized. Further, a gate and a well in a cross-coupled type sense amplifier using FD-SOI MOSTs are connected. By this means, a threshold value dynamically changes and high-speed sensing operation can be realized.
摘要翻译：提供能够以1V以下工作的高速低电压DRAM存储单元和阵列外围电路。 DRAM单元由利用FD-SOI MOST结构的存储单元晶体管和平面电容器组成。由于没有结漏电流，消除了存储电荷的损失，并且可以实现低电压操作。此外，使用FD-SOI MOST的交叉耦合型读出放大器中的栅极和阱连接。通过这种方式，阈值动态地变化，并且可以实现高速感测操作。

48. 发明授权

US07772917B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07772917B2
公开(公告)日：2010-08-10
申请号：US12412781
申请日：2009-03-27
申请人： Kiyoo Itoh , HIroyuki Mizuno
发明人： Kiyoo Itoh , HIroyuki Mizuno
IPC分类号： H03K19/003
CPC分类号： G11C5/146 , G05F3/205 , G11C5/147 , H01L27/092 , H02M3/073 , H03K19/0013 , H03K19/0016 , H03K19/00315
摘要： The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.
摘要翻译：当电源接通时，在正常操作期间以及当电源电压被切断时，控制具有低阈值电压MOSFET的CMOS电路的阱电压。因此，CMOS电路可以以更低的功耗稳定地运行，因为当将电源电压施加到CMOS电路时或者当电源电压被切断时，锁存减小，并且在正常操作期间亚阈值电流减小。

49. 发明授权

US07750668B2 Semiconductor integrated circuit device having power reduction mechanism 失效
标题翻译：具有降压机构的半导体集成电路装置
公开(公告)号：US07750668B2
公开(公告)日：2010-07-06
申请号：US11979100
申请日：2007-10-31
申请人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
发明人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
IPC分类号： H03K19/003 , G05F1/10 , G06F1/32
CPC分类号： H01L27/0207 , G06F1/3203 , G11C5/14 , H01L27/0218 , H03K3/356113 , H03K19/0013 , H03K19/0016 , H03K19/01721
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
摘要翻译：半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。逻辑门连接到第一电势点和第二电位点。半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值逻辑门。该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

50. 发明授权

US07719870B2 Storage device 有权
标题翻译：储存设备
公开(公告)号：US07719870B2
公开(公告)日：2010-05-18
申请号：US11976532
申请日：2007-10-25
申请人： Satoru Hanzawa , Kiyoo Itoh , Hideyuki Matsuoka , Motoyasu Terao , Takeshi Sakata
发明人： Satoru Hanzawa , Kiyoo Itoh , Hideyuki Matsuoka , Motoyasu Terao , Takeshi Sakata
IPC分类号： G11C7/00
CPC分类号： H01L27/101 , G11C7/12 , G11C8/10 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/0054 , G11C2013/0078 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected wordline conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.
摘要翻译：本发明的目的是避免在由选择的字线上的所有存储单元中的选择晶体管导通的存储单元中构成的存储器阵列中的未选择的数据线被驱动，每个存储器单元使用依赖于可变电阻的存储元件和选择晶体管。为了实现该目的，提供了与数据线并行的源极线，布置用于等电位驱动两者的预充电电路和用于选择性地驱动源极线的电路。由于该配置，仅在由行解码器选择的单元中创建电流路径，并且可以生成列解码器，并且可以生成读出信号。因此，与常规型相比，可以实现诸如相变存储器的低功率，低噪声和更高度集成的非易失性存储器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式