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41. 发明授权

US06258649B1 Semiconductor integrated circuit device and method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06258649B1
公开(公告)日：2001-07-10
申请号：US09389231
申请日：1999-09-03
申请人： Yoshitaka Nakamura , Masayoshi Hirasawa , Isamu Asano , Tsuyoshi Tamaru , Satoru Yamada , Keizo Kawakita , Toshihiro Sekiguchi , Yoshitaka Tadaki , Takuya Fukuda
发明人： Yoshitaka Nakamura , Masayoshi Hirasawa , Isamu Asano , Tsuyoshi Tamaru , Satoru Yamada , Keizo Kawakita , Toshihiro Sekiguchi , Yoshitaka Tadaki , Takuya Fukuda
IPC分类号： H01L218234
CPC分类号： H01L27/10894 , H01L21/28518 , H01L21/31612 , H01L21/76801 , H01L21/76816 , H01L21/76828 , H01L21/76843 , H01L21/76855 , H01L23/53223 , H01L27/10882 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： In order to improve connection reliability of a feeding interconnection connected to an electrode of each of the information storage capacitive elements of a DRAM, the formation of a through hole for connecting the information storage capacitive element formed over each memory cell selection MISFET and a feeding interconnection is performed in a process different from that for the formation of a through hole for connecting an interconnection of a second wiring layer in a peripheral circuit, which is formed over the information storage capacitive element and an interconnection corresponding to a first wiring layer.
摘要翻译：为了提高连接到DRAM的每个信息存储电容元件的电极的馈电互连的连接可靠性，形成用于连接在每个存储单元选择MISFET上形成的信息存储电容元件的通孔和馈电互连在与形成用于连接在信息存储电容元件上形成的外围电路中的第二布线层的互连的通孔和形成用于连接对应于第一布线层的互连的通孔中。

42. 发明授权

US4086815A Device for use in sensing pressures 失效
标题翻译：用于感测压力的装置
公开(公告)号：US4086815A
公开(公告)日：1978-05-02
申请号：US708251
申请日：1976-07-23
申请人： Isamu Asano , Mitsuru Tamai , Tadanori Yuhara , Takeshi Yasuhara
发明人： Isamu Asano , Mitsuru Tamai , Tadanori Yuhara , Takeshi Yasuhara
IPC分类号： G01L9/00 , G01L13/02 , G01L9/12
CPC分类号： G01L13/025 , G01L9/007 , G01L9/0072
摘要： A pressure sensing device is disclosed having the pressure sensing diaphragm positioned in a housing which is not stressed or enlarged by large static pressure. The housing is attached within a recess of a larger casing by means of a support diaphragm. The recesses are communicated with the interior of the housing by passages therethrough to equalize the pressure inside and outside the housing. The outer side of each casing forms a pressure reception chamber with a respective pressure receiving diaphragm. The latter chambers communicate with the recess via passages in the casing. The space between the pressure sensitive diaphragm and each pressure receiving diaphragm, including the housing interior chamber, the housing passage, the casing recess, the casing passage and the pressure receptive chamber, is filled with a fluid. The construction and filling is such that overpressure on one pressure receiving diaphram causes the entire housing to move toward the inner wall of the casing. However the latter diaphragm closes with the outer wall of the casing before the housing contacts the casing inner wall.
摘要翻译：公开了一种压力感测装置，其具有位于壳体中的压力感测膜片，该壳体不受大的静压力的压力或增大。壳体通过支撑膜片附接在较大壳体的凹部内。凹槽通过其中的通道与壳体的内部连通，以均衡壳体内外的压力。每个壳体的外侧形成具有相应的压力接收膜片的受压室。后者室通过壳体中的通道与凹槽连通。包括壳体内部室，壳体通道，壳体凹部，壳体通道和压力接收室之间的压力敏感隔膜和每个受压隔膜之间的空间填充有流体。施工和填充使得在一个受压的压力下的超压使得整个壳体朝向壳体的内壁移动。然而，在壳体接触壳体内壁之前，后一个隔膜与外壳的外壁相连。

43. 发明授权

US08637843B2 Semiconductor device including phase change material and method of manufacturing same 失效
标题翻译：包括相变材料的半导体器件及其制造方法
公开(公告)号：US08637843B2
公开(公告)日：2014-01-28
申请号：US13370693
申请日：2012-02-10
申请人： Isamu Asano
发明人： Isamu Asano
IPC分类号： H01L29/02
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/144
摘要： Disclosed herein is a device that includes: an interlayer insulation film having a through hole; and a phase change storage element provided in the through hole. The phase change storage element includes: an outer electrode being a conductive film of cylindrical shape and being formed along an inner wall of the through hole; a buffer insulation film being an insulation film of cylindrical shape and being formed along an inner wall of the outer electrode, an upper end of the buffer insulation film being recessed in part to form a recess; a phase change film filling an interior of the recess; and an inner electrode being a conductive film formed along an inner wall of the buffer insulation film including a surface of the phase change film.
摘要翻译：本文公开了一种装置，其包括：具有通孔的层间绝缘膜; 以及设置在通孔中的相变存储元件。相变存储元件包括：外电极，其是圆柱形导电膜，沿着通孔的内壁形成; 缓冲绝缘膜是圆柱形绝缘膜，沿着外电极的内壁形成，缓冲绝缘膜的上端部分地凹入以形成凹部; 填充所述凹部内部的相变膜; 并且内部电极是沿着包括相变膜的表面的缓冲绝缘膜的内壁形成的导电膜。

44. 发明授权

US07671356B2 Electrically rewritable non-volatile memory element and method of manufacturing the same 有权
标题翻译：电可重写非易失性存储元件及其制造方法
公开(公告)号：US07671356B2
公开(公告)日：2010-03-02
申请号：US11265275
申请日：2005-11-03
申请人： Isamu Asano , Tyler A. Lowrey
发明人： Isamu Asano , Tyler A. Lowrey
IPC分类号： H01L47/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C2213/52 , H01L45/06 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： A non-volatile memory element comprising a bottom electrode 12, a top electrode 17 provided on the bottom electrode 12, and a recording layer 18 containing phase change material connected between the bottom electrode 12 and the top electrode 17. In accordance with this invention, the top electrode 17 is in contact with a growth initiation surface 18a of the recording layer 17. This structure can be obtained by forming the top electrode 17 before the recording layer 18, resulting in a three-dimensional structure. This decreases heat dissipation to the bit line without increasing the thickness of the recording layer 18.
摘要翻译：包括底部电极12，设置在底部电极12上的顶部电极17和包含连接在底部电极12和顶部电极17之间的相变材料的记录层18的非易失性存储元件。根据本发明，顶部电极17与记录层17的生长起始表面18a接触。这种结构可以通过在记录层18之前形成顶部电极17而获得，从而形成三维结构。这降低了对位线的散热，而不增加记录层18的厚度。

45. 发明授权

US07554147B2 Memory device and manufacturing method thereof 失效
标题翻译：存储器件及其制造方法
公开(公告)号：US07554147B2
公开(公告)日：2009-06-30
申请号：US11374074
申请日：2006-03-14
申请人： Isamu Asano , Tsuyoshi Kawagoe , Kiyoshi Nakai , Yukio Fuji , Kazuhiko Kajigaya
发明人： Isamu Asano , Tsuyoshi Kawagoe , Kiyoshi Nakai , Yukio Fuji , Kazuhiko Kajigaya
IPC分类号： H01L27/108
CPC分类号： G11C13/0004 , G11C11/005 , H01L27/10894 , H01L27/10897 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.
摘要翻译：其中安装了DRAM和相变存储器（PCRAM）的存储器件具有形成在与DRAM位线共享的导电层上的DRAM位线，PCRAM位线或PCRAM源线，以及读出放大器连接在DRAM位线和PCRAM位线之间。存储器件还具有设置在DRAM位线的上层上的电容元件和设置在PCRAM位线的上层上的相变元件。电容元件的下电极和相变存储元件的下电极形成在共用导电层上。

46. 发明授权

US07333363B2 Semiconductor storage apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US07333363B2
公开(公告)日：2008-02-19
申请号：US11409088
申请日：2006-04-24
申请人： Kiyoshi Nakai , Kazuhiko Kajigaya , Isamu Asano
发明人： Kiyoshi Nakai , Kazuhiko Kajigaya , Isamu Asano
IPC分类号： G11C14/00
CPC分类号： G11C11/005 , G11C7/20 , G11C11/4072 , G11C13/0004
摘要： Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.
摘要翻译：公开了一种半导体存储装置，其中两种存储器，即易失性存储器和非易失性存储器安装在一个芯片上。 DRAM存储器阵列的数据在进入数据保持模式之前或在断电之前被保存在非易失性存储器的相应区域中，并且数据从非易失性存储器的区域传送到DRAM存储器阵列数据保留模式或上电。对DRAM存储器阵列进行正常读/写访问，而数据保留位于非易失性存储器的区域。

47. 发明申请

US20070141786A1 Method of manufacturing non-volatile memory element 审中-公开
标题翻译：制造非易失性存储元件的方法
公开(公告)号：US20070141786A1
公开(公告)日：2007-06-21
申请号：US11637069
申请日：2006-12-12
申请人： Tsuyoshi Kawagoe , Isamu Asano
发明人： Tsuyoshi Kawagoe , Isamu Asano
IPC分类号： H01L21/336
CPC分类号： H01L45/1658 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1625
摘要： A method of manufacturing a non-volatile memory element in the present invention comprises a first step for forming an adhesion layer on an interlayer insulating film so that an electrical connection is established with a lower electrode, a second step for forming a recording layer containing a phase change material on the adhesion layer, a third step for forming an upper electrode that is electrically connected to the recording layer, and a fourth step for diffusing in the recording layer some of the adhesion layer positioned between at least the lower electrode and the recording layer.
摘要翻译：本发明的非易失性存储元件的制造方法包括：在层间绝缘膜上形成粘接层的第一工序，与下部电极形成电连接;第二工序，形成含有形成与记录层电连接的上部电极的第三工序，以及在记录层中扩散位于至少下部电极与记录材料之间的一部分粘合层的第四工序层。

48. 发明申请

US20070123018A1 Electrically rewritable non-volatile memory element and method of manufacturing the same 有权
标题翻译：电可重写非易失性存储元件及其制造方法
公开(公告)号：US20070123018A1
公开(公告)日：2007-05-31
申请号：US11594747
申请日：2006-11-09
申请人： Isamu Asano
发明人： Isamu Asano
IPC分类号： H01L21/44
CPC分类号： H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A non-volatile memory element includes a lower electrode, an upper electrode, a recording layer arranged between the lower electrode and the upper electrode and containing a phase change material, and a bit line directly arranged on the upper electrode. The bit line is formed to be offset to the recording layer. With this arrangement, a contact area between the recording layer and the upper electrode and a contact area between the upper electrode and the bit line can be reduced without providing an interlayer insulation film between the upper electrode and the bit line. Thus, heat radiation to the bit line can be suppressed while the upper electrode and the bit line are connected without using a through-hole.
摘要翻译：非易失性存储元件包括下电极，上电极，布置在下电极和上电极之间并包含相变材料的记录层，以及直接布置在上电极上的位线。位线形成为偏移到记录层。通过这种布置，可以减小记录层与上部电极之间的接触面积以及上部电极和位线之间的接触面积，而不会在上部电极和位线之间设置层间绝缘膜。因此，在不使用通孔的同时连接上电极和位线的同时可以抑制到位线的热辐射。

49. 发明申请

US20070063180A1 Electrically rewritable non-volatile memory element and method of manufacturing the same 审中-公开
标题翻译：电可重写非易失性存储元件及其制造方法
公开(公告)号：US20070063180A1
公开(公告)日：2007-03-22
申请号：US11516510
申请日：2006-09-07
申请人： Isamu Asano , Natsuki Sato , Kiyoshi Nakai
发明人： Isamu Asano , Natsuki Sato , Kiyoshi Nakai
IPC分类号： H01L29/04
CPC分类号： H01L27/2436 , G11C2213/52 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675 , H01L45/1683
摘要： A non-volatile memory element includes a recording layer that includes a phase change material, a lower electrode provided in contact with the recording layer, an upper electrode provided in contact with a portion of the upper surface of the recording layer, a protective insulation film provided in contact with the other portion of the upper surface of the recording layer, and an interlayer insulation film provided on the protective insulation film. High thermal efficiency can thereby be obtained because the size of the area of contact between the recording layer and the upper electrode is reduced. Providing the protective insulation film between the interlayer insulation film and the upper surface of the recording layer makes it possible to reduce damage sustained by the recording layer during patterning of the recording layer or during formation of the through-hole for exposing a portion of the recording layer.
摘要翻译：非易失性存储元件包括记录层，其包括相变材料，与记录层接触地设置的下电极，设置成与记录层的上表面的一部分接触的上电极，保护绝缘膜设置成与记录层的上表面的另一部分接触，以及设置在保护绝缘膜上的层间绝缘膜。由于记录层和上部电极之间的接触面积的尺寸减小，因此可获得高热效率。在层间绝缘膜和记录层的上表面之间提供保护性绝缘膜使得可以减少在记录层的图案化期间或在用于曝光记录部分的通孔的形成期间记录层所承受的损伤层。

50. 发明授权

US07145193B2 Semiconductor integrated circuit device and process for manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07145193B2
公开(公告)日：2006-12-05
申请号：US10470573
申请日：2002-08-29
申请人： Yoshitaka Nakamura , Isamu Asano , Keizou Kawakita , Satoru Yamada
发明人： Yoshitaka Nakamura , Isamu Asano , Keizou Kawakita , Satoru Yamada
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L21/76802 , H01L21/76877 , H01L23/5226 , H01L27/10814 , H01L27/10882 , H01L2924/0002 , H01L2924/00
摘要： In a peripheral circuit region of a DRAM, two connection holes, for connecting a first layer line and a second layer line electrically are opened separately in two processes. After forming the connection holes, plugs are formed in the respective connection holes.
摘要翻译：在DRAM的外围电路区域中，用于连接第一层线路和第二层线路的两个连接孔在两个工序中分开开放。在形成连接孔之后，在相应的连接孔中形成插头。

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