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    • 45. 发明申请
    • MULTILAYER WIRING BOARD
    • 多层接线板
    • US20050087364A1
    • 2005-04-28
    • US10711638
    • 2004-09-29
    • Kazuhiro Umemoto
    • Kazuhiro Umemoto
    • H05K3/34H01L21/60H01L23/12H01L23/498H05K1/11H05K3/46H05K1/18H01L23/488
    • H05K1/111H01L23/49816H01L23/49838H01L2224/16H01L2924/01078H05K3/3436H05K3/3452H05K2201/09381H05K2201/099H05K2201/10674Y02P70/611
    • To prevent, in a multilayer wiring board to which a semiconductor chip is flip-chip bonded, occurrence of cracks in the board at portions adjacent to electrode pads due to a difference in thermal expansion coefficient between the semiconductor chip and the board. A multilayer wiring board (20) of the present invention has features that electrode pads (22) corresponding to electrodes of a semiconductor chip (25) located near an outer periphery (29) of the semiconductor chip each have an oblong shape, openings (35) of a solder resist (23) are each smaller than the oblong shape, and the center (B) of the opening is located to be offset from the center (A) of the oblong shape by a distance (L4) in a direction (30) toward the center of the semiconductor chip. Therefore, in the multilayer wiring board of the present invention, thermal stresses applied to portions (L3) of the electrode pads (22) on the board near the outer periphery of the semiconductor chip are relaxed. Consequently, the multilayer wiring board of the present invention can prevent occurrence of cracks in the board at portions adjacent to the electrode pads near the outer periphery of the semiconductor chip due to a difference in thermal expansion coefficient between the semiconductor chip and the board.
    • 为了防止由于半导体芯片与板之间的热膨胀系数的差异,在半导体芯片被倒装芯片接合的多层布线板中,与电极焊盘相邻的部分在板上产生裂纹。 本发明的多层布线基板(20)的特征在于,与位于半导体芯片的外周(29)附近的半导体芯片(25)的电极对应的电极焊盘(22)具有长方形形状,开口(35 阻焊剂(23)的长度方向的距离小于长方形,开口的中心(B)位于从长方形的中心(A)偏离距离(L 4)的方向 (30)朝向半导体芯片的中心。 因此,在本发明的多层布线基板中,对半导体芯片的外周附近的电路板(22)的部分(L 3)施加的热应力被放宽。 因此,本发明的多层布线基板由于半导体芯片和基板之间的热膨胀系数的差异,能够防止在半导体芯片的外周附近的与电极焊盘相邻的部分处发生裂纹。
    • 49. 发明授权
    • Multilayer wiring board
    • 多层接线板
    • US07078629B2
    • 2006-07-18
    • US10711638
    • 2004-09-29
    • Kazuhiro Umemoto
    • Kazuhiro Umemoto
    • H05K1/16
    • H05K1/111H01L23/49816H01L23/49838H01L2224/16H01L2924/01078H05K3/3436H05K3/3452H05K2201/09381H05K2201/099H05K2201/10674Y02P70/611
    • To prevent, in a multilayer wiring board to which a semiconductor chip is flip-chip bonded, occurrence of cracks in the board at portions adjacent to electrode pads due to a difference in thermal expansion coefficient between the semiconductor chip and the board. A multilayer wiring board (20) of the present invention has features that electrode pads (22) corresponding to electrodes of a semiconductor chip (25) located near an outer periphery (29) of the semiconductor chip each have an oblong shape, openings (35) of a solder resist (23) are each smaller than the oblong shape, and the center (B) of the opening is located to be offset from the center (A) of the oblong shape by a distance (L4) in a direction (30) toward the center of the semiconductor chip. Therefore, in the multilayer wiring board of the present invention, thermal stresses applied to portions (L3) of the electrode pads (22) on the board near the outer periphery of the semiconductor chip are relaxed. Consequently, the multilayer wiring board of the present invention can prevent occurrence of cracks in the board at portions adjacent to the electrode pads near the outer periphery of the semiconductor chip due to a difference in thermal expansion coefficient between the semiconductor chip and the board.
    • 为了防止由于半导体芯片与板之间的热膨胀系数的差异,在半导体芯片被倒装芯片接合的多层布线板中,与电极焊盘相邻的部分在板上产生裂纹。 本发明的多层布线基板(20)的特征在于,与位于半导体芯片的外周(29)附近的半导体芯片(25)的电极对应的电极焊盘(22)具有长方形形状,开口(35 阻焊剂(23)的长度方向的距离小于长方形,开口的中心(B)位于从长方形的中心(A)偏离距离(L 4)的方向 (30)朝向半导体芯片的中心。 因此,在本发明的多层布线基板中,对半导体芯片的外周附近的电路板(22)的部分(L 3)施加的热应力被放宽。 因此,本发明的多层布线基板由于半导体芯片和基板之间的热膨胀系数的差异,能够防止在半导体芯片的外周附近的与电极焊盘相邻的部分处发生裂纹。