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    • 41. 发明授权
    • Method of forming shallow doped junctions having a variable profile gradation of dopants
    • 形成具有可变轮廓层级的掺杂剂的浅掺杂结的方法
    • US07179703B2
    • 2007-02-20
    • US11259489
    • 2005-10-25
    • Fernando GonzalezRandhir Thakur
    • Fernando GonzalezRandhir Thakur
    • H01L21/8238
    • H01L29/6659H01L21/2236H01L21/26513H01L21/2652H01L29/66575H01L29/7833H01L29/7836Y10S257/90
    • Disclosed are methods for forming a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention includes first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. Next, a low ion velocity and low energy ion bombardment plasma doping or PLAD operation is conducted to provide a highly doped inner portion of a shallow junction. In a further step, a higher ion velocity and energy conventional ion bombardment implantation doping operation is conducted using a medium power implanter to extend the shallow junction boundaries with a lightly doped outer portion. In various embodiments, the doping steps can be performed in reverse order. In addition, an anneal step can be performed after any doping operation.
    • 公开了用于形成具有可变浓度分布层级的掺杂剂的浅结的方法。 本发明的方法包括首先提供和掩蔽要在其上形成浅结的过程中集成电路晶片上的表面。 接下来,进行低离子速度和低能离子轰击等离子体掺杂或PLAD操作以提供浅结的高掺杂内部部分。 在另一步骤中,使用中功率注入机进行较高的离子速度和能量常规的离子轰击注入掺杂操作,以用轻掺杂的外部部分延伸浅结边界。 在各种实施例中,可以以相反的顺序执行掺杂步骤。 此外,可以在任何掺杂操作之后执行退火步骤。
    • 50. 发明授权
    • Shallow doped junctions with a variable profile gradation of dopants
    • 具有可变轮廓层次的掺杂剂的浅掺杂结
    • US06717211B2
    • 2004-04-06
    • US09981549
    • 2001-10-17
    • Fernando GonzalezRandhir Thakur
    • Fernando GonzalezRandhir Thakur
    • H01L2976
    • H01L29/6659H01L21/2236H01L21/26513H01L21/2652H01L29/66575H01L29/7833H01L29/7836Y10S257/90
    • An electrical device including a shallow junction with a variable concentration profile gradation of dopants. The junction is suitable for forming source and drain regions in MOS transistors, especially where a contact or interconnect is intended to engage the source and drain regions. The variable concentration profile gradation of dopants helps to maintain proper threshold voltage levels and reduces reverse bias current leakage. The electrical device includes a semiconductor substrate having a top surface, a gate region overlapping a portion of the semiconductor substrate, and a source/drain region disposed within the semiconductor substrate. The source/drain region includes an inner portion and an outer portion, wherein the inner portion extends from the top surface of the semiconductor substrate to a bottom periphery and does not underlap the gate region, and the outer portion extends from the bottom periphery of the inner portion and underlaps the gate region. An electrical insulation layer is situated upon the gate region and overlaps the source/drain region.
    • 包括具有可变浓度分布层级的掺杂剂的浅结的电气装置。 该结适用于在MOS晶体管中形成源极和漏极区域,特别是在接触或互连用于接合源极和漏极区域的情况下。 掺杂剂的可变浓度分布层次有助于保持适当的阈值电压电平并减少反向偏置电流泄漏。 电气装置包括具有顶表面,与半导体衬底的一部分重叠的栅极区域和设置在半导体衬底内的源极/漏极区域的半导体衬底。 源极/漏极区域包括内部部分和外部部分,其中内部部分从半导体衬底的顶表面延伸到底部周边,并且不会使栅极区域下凹,并且外部部分从底部周边延伸 内部部分并且使栅极区域重叠。 电绝缘层位于栅极区上并与源极/漏极区重叠。