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41. 发明授权

US08680644B2 Semiconductor device and method for making same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08680644B2
公开(公告)日：2014-03-25
申请号：US13083879
申请日：2011-04-11
申请人： Kangguo Cheng , Bruce B. Doris , Tenko Yamashita , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Tenko Yamashita , Ying Zhang
IPC分类号： H01L21/762
CPC分类号： H01L21/28123 , H01L21/76224 , H01L21/84 , H01L27/11 , H01L27/1203
摘要： A semiconductor device including a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity.
摘要翻译：一种半导体器件，包括具有至少一个氮化物材料衬里隔离腔的衬底; 以及含有铪的电介质填充物，其至少部分地包含在并且至少部分地覆盖所述至少一个氮化物衬里隔离腔的至少一部分。

42. 发明授权

US08673735B2 Semiconductor device and method for making same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08673735B2
公开(公告)日：2014-03-18
申请号：US13617464
申请日：2012-09-14
申请人： Kangguo Cheng , Bruce B. Doris , Tenko Yamashita , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Tenko Yamashita , Ying Zhang
IPC分类号： H01L21/76
CPC分类号： H01L21/28123 , H01L21/76224 , H01L21/84 , H01L27/11 , H01L27/1203
摘要： A semiconductor device includes a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity.
摘要翻译：半导体器件包括具有至少一个氮化物材料衬里隔离腔的衬底; 以及含有铪的电介质填充物，其至少部分地包含在并且至少部分地覆盖所述至少一个氮化物衬里隔离腔的至少一部分。

43. 发明授权

US08354331B2 Multiplying pattern density by single sidewall imaging transfer 有权
公开(公告)号：US08354331B2
公开(公告)日：2013-01-15
申请号：US12628686
申请日：2009-12-01
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L21/20 , H01L21/00
CPC分类号： H01L29/66795 , H01L21/0337 , H01L21/3086 , H01L29/66818
摘要： A method for fabricating an integrated circuit includes patterning a mandrel over a layer to be patterned. Dopants are implanted into exposed sidewalls of the mandrel to form at least two doped layers having at least one undoped region adjacent to the doped layers. The doped layers are selectively etched away to form pillars from the undoped regions. The layer to be patterned is etched using the pillars as an etch mask to form features for an integrated circuit device. A semiconductor device is also disclosed.

44. 发明申请

US20110291188A1 STRAINED FINFET 审中-公开
标题翻译：应变FINFET
公开(公告)号：US20110291188A1
公开(公告)日：2011-12-01
申请号：US12787383
申请日：2010-05-25
申请人： Kangguo Cheng , Bruce B. Doris , Xuefeng Hua , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Xuefeng Hua , Ying Zhang
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7853
摘要： A FinFET is described incorporating at least two fins extending from a common Si containing layer and epitaxial material grown from the common layer and from sidewalls of the fins to introduce strain to the common layer and the fins to increase carrier mobility.
摘要翻译：描述了FinFET，其包括从共同的含Si层延伸的至少两个翅片和从公共层和翅片的侧壁生长的外延材料，以将应变引入公共层和翅片以增加载流子迁移率。

45. 发明申请

US20110175163A1 FinFET WITH THIN GATE DIELECTRIC LAYER 有权
标题翻译：具有薄栅介质层的FinFET
公开(公告)号：US20110175163A1
公开(公告)日：2011-07-21
申请号：US12688347
申请日：2010-01-15
申请人： Eduard A. Cartier , Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Eduard A. Cartier , Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/785 , H01L29/66795
摘要： A semiconductor device is provided that in one embodiment includes at least one semiconductor fin structure atop a dielectric surface, the semiconductor fin structure including a channel region of a first conductivity type and source and drain regions of a second conductivity type, in which the source and drain regions are present at opposing ends of the semiconductor fin structure. A high-k gate dielectric layer having a thickness ranging from 1.0 nm to 5.0 nm is in direct contact with the channel of the semiconductor fin structure. At least one gate conductor layer is in direct contact with the high-k gate dielectric layer. A method of forming the aforementioned device is also provided.
摘要翻译：提供了一种半导体器件，其在一个实施例中包括在电介质表面上方的至少一个半导体鳍结构，所述半导体鳍结构包括第一导电类型的沟道区和第二导电类型的源区和漏区，漏区存在于半导体鳍结构的相对端。具有1.0nm至5.0nm厚度的高k栅介质层与半导体鳍结构的沟道直接接触。至少一个栅极导体层与高k栅极电介质层直接接触。还提供了一种形成上述装置的方法。

46. 发明申请

US20110127582A1 MULTIPLYING PATTERN DENSITY BY SINGLE SIDEWALL IMAGING TRANSFER 有权
标题翻译：通过单边形图像传输实现图案密度的多样化
公开(公告)号：US20110127582A1
公开(公告)日：2011-06-02
申请号：US12628686
申请日：2009-12-01
申请人： KANGGUO CHENG , Bruce B. Doris , Ying Zhang
发明人： KANGGUO CHENG , Bruce B. Doris , Ying Zhang
IPC分类号： H01L29/772 , H01L21/306 , H01L21/20
CPC分类号： H01L29/66795 , H01L21/0337 , H01L21/3086 , H01L29/66818
摘要： A method for fabricating an integrated circuit includes patterning a mandrel over a layer to be patterned. Dopants are implanted into exposed sidewalls of the mandrel to foam at least two doped layers having at least one undoped region adjacent to the doped layers. The doped layers are selectively etched away to form pillars from the undoped regions. The layer to be patterned is etched using the pillars as an etch mask to form features for an integrated circuit device. A semiconductor device is also disclosed.
摘要翻译：一种用于制造集成电路的方法包括在待图案化的层上图案化心轴。将掺杂剂注入到心轴的暴露的侧壁中以使至少两个具有至少一个与掺杂层相邻的未掺杂区的掺杂层发泡。选择性地蚀刻去除掺杂层以从未掺杂的区域形成柱。使用柱作为蚀刻掩模蚀刻待图案化的层以形成用于集成电路器件的特征。还公开了一种半导体器件。

47. 发明申请

US20100297837A1 Implantation using a hardmask 有权
标题翻译：使用硬掩模进行植入
公开(公告)号：US20100297837A1
公开(公告)日：2010-11-25
申请号：US12469710
申请日：2009-05-21
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L21/8234 , H01L21/266
CPC分类号： H01L21/266 , H01L21/823892
摘要： A method for processing CMOS wells, and performing multiple ion implantations with the use of a single hard mask is disclosed. The method includes forming and patterning a hardmask over a substrate, whereby the hardmask attains a first opening. The substrate may be a semiconductor substrate. The method further includes performing a first ion implantation, during which, outside the first opening the hardmask is essentially preventing ions from reaching the substrate. The method further involves the application of a photoresist in such a manner that the photoresist is covering the hardmask, and it is also filling up the first opening. This is followed by using the photoresist to pattern the hardmask, whereby the hardmask attains a second opening. The method further includes performing a second ion implantation, during which, outside the second opening, the hardmask and the photoresist, which fills the first opening, are essentially preventing ions from reaching the substrate. The two ion implantations may be used to form the two type of CMOS wells.
摘要翻译：公开了一种用于处理CMOS阱的方法，并且使用单个硬掩模执行多个离子注入。该方法包括在衬底上形成和图案化硬掩模，由此硬掩模获得第一开口。衬底可以是半导体衬底。该方法还包括执行第一离子注入，其间在第一开口外部，硬掩模基本上防止离子到达衬底。该方法还涉及以光致抗蚀剂覆盖硬掩模的方式施加光致抗蚀剂，并且其还填充第一开口。然后使用光致抗蚀剂来模拟硬掩模，由此硬掩模获得第二开口。该方法还包括执行第二离子注入，其间在第二开口外部，填充第一开口的硬掩模和光致抗蚀剂基本上防止离子到达衬底。两个离子注入可用于形成两种类型的CMOS阱。

48. 发明申请

US20130012009A1 METHOD FOR SELF ALIGNED METAL GATE CMOS 审中-公开
标题翻译：自对准金属栅CMOS的方法
公开(公告)号：US20130012009A1
公开(公告)日：2013-01-10
申请号：US13617528
申请日：2012-09-14
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L21/283
CPC分类号： H01L21/823842 , H01L29/66545 , H01L29/7833 , H01L29/7843 , H01L2924/13085 , H01L2924/13092
摘要： A semiconductor device is formed by first providing a dual gate semiconductor device structure having FET pair precursors, which includes an nFET precursor and a pFET precursor, wherein each of the nFET precursor and the pFET precursor includes a dummy gate structure. At least one protective layer is deposited across the FET pair precursors, leaving the dummy gate structures exposed. The dummy gate structure is removed from one of the nFET precursor and the pFET precursor to create therein one of an nFET gate hole and a pFET gate hole, respectively. A fill is deposited into the formed one of the nFET gate hole and the pFET gate.
摘要翻译：半导体器件通过首先提供具有FET对前体的双栅极半导体器件结构形成，其包括nFET前体和pFET前体，其中nFET前体和pFET前体中的每一个包括伪栅极结构。至少一个保护层沉积在FET对前体之间，留下伪栅极结构。从nFET前体和pFET前体之一去除伪栅极结构，以在其中分别形成nFET栅极孔和pFET栅极孔中的一个。填充物沉积在形成的nFET栅极孔和pFET栅极之一中。

49. 发明申请

US20130001702A1 ENHANCING MOSFET PERFORMANCE BY OPTIMIZING STRESS PROPERTIES 审中-公开
标题翻译：通过优化应力特性提高MOSFET的性能
公开(公告)号：US20130001702A1
公开(公告)日：2013-01-03
申请号：US13613081
申请日：2012-09-13
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L27/092
CPC分类号： H01L29/7843 , H01L21/26586 , H01L21/31155 , H01L21/823807 , H01L21/823864 , H01L29/6659 , H01L29/7833
摘要： A device and method for improving performance of a transistor includes gate structures formed on a substrate having a spacing therebetween. The gate structures are formed in an operative relationship with active areas formed in the substrate. A stress liner is formed on the gate structures. An angled ion implantation is applied to the stress liner such that ions are directed at vertical surfaces of the stress liner wherein portions of the stress liner in contact with the active areas are shielded from the ions due to a shadowing effect provided by a height and spacing between adjacent structures.
摘要翻译：用于提高晶体管性能的器件和方法包括形成在其间具有间隔的衬底上的栅极结构。栅极结构形成在与衬底中形成的有源区域的操作关系中。在栅极结构上形成应力衬垫。角度离子注入施加到应力衬垫上，使得离子被引导到应力衬垫的垂直表面，其中应力衬垫与有源区域接触的部分由于由高度和间隔提供的阴影效应而被屏蔽离子相邻结构之间。

50. 发明授权

US08268729B2 Smooth and vertical semiconductor fin structure 有权
标题翻译：平滑和垂直的半导体鳍结构
公开(公告)号：US08268729B2
公开(公告)日：2012-09-18
申请号：US12195691
申请日：2008-08-21
申请人： Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ying Zhang
IPC分类号： H01L21/302 , H01L21/324
CPC分类号： H01L21/30608 , H01L29/045 , H01L29/66795
摘要： A method for processing a semiconductor fin structure is disclosed. The method includes thermal annealing a fin structure in an ambient containing an isotope of hydrogen. Following the thermal annealing step, the fin structure is etched in a crystal-orientation dependent, self-limiting, manner. The crystal-orientation dependent etch may be selected to be an aqueous solution containing ammonium hydroxide (NH4OH). The completed fin structure has smooth sidewalls and a uniform thickness profile. The fin structure sidewalls are {110} planes.
摘要翻译：公开了一种半导体鳍片结构的处理方法。该方法包括在含有氢同位素的环境中对翅片结构进行热退火。在热退火步骤之后，鳍结构被蚀刻成晶体取向的自限制的方式。取决于晶体取向的蚀刻可以选择为含有氢氧化铵（NH 4 OH）的水溶液。完成的翅片结构具有平滑的侧壁和均匀的厚度轮廓。翅片结构侧壁是{110}平面。

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