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    • 42. 发明申请
    • DUTY CYCLE CORRECTOR
    • 占空比校正器
    • US20070241799A1
    • 2007-10-18
    • US11403453
    • 2006-04-13
    • Alessandro MinzoniJonghee Han
    • Alessandro MinzoniJonghee Han
    • H03K3/017
    • H03K5/1565
    • A duty cycle corrector includes a first controllable delay, a second controllable delay, a phase detector, and a compensation circuit. The first controllable delay is configured to delay a first signal to provide a second signal. The second controllable delay is configured to delay the second signal to provide a third signal. The phase detector is configured to adjust the first controllable delay and the second controllable delay to phase lock the third signal to the first signal. The compensation circuit is configured to compensate for a mismatch between the first controllable delay and the second controllable delay to provide a fourth signal in response to the first signal and a fifth signal approximately 180 degrees out of phase with the fourth signal in response to the second signal.
    • 占空比校正器包括第一可控延迟,第二可控延迟,相位检测器和补偿电路。 第一可控延迟被配置为延迟第一信号以提供第二信号。 第二可控延迟被配置为延迟第二信号以提供第三信号。 相位检测器被配置为调整第一可控延迟和第二可控延迟以将第三信号锁相到第一信号。 补偿电路被配置为补偿第一可控延迟和第二可控延迟之间的失配,以响应于第一信号提供第四信号,并响应于第二信号与第四信号大致180度异相,响应于第二信号 信号。
    • 43. 发明授权
    • Input buffer circuit including reference voltage monitoring circuit
    • 输入缓冲电路,包括参考电压监控电路
    • US07064586B2
    • 2006-06-20
    • US10739097
    • 2003-12-19
    • Jung Pill KimJonghee Han
    • Jung Pill KimJonghee Han
    • H03K5/153H03K5/22
    • H03K19/00384H03K19/018528
    • A buffer circuit includes a differential amplifier, a buffering inverter, and a reference voltage monitoring circuit. The differential amplifier has a reference voltage and a current source as inputs. The buffering inverter has an output of the differential amplifier as an input. The reference voltage monitoring circuit includes two transistors and a second current source. An output of the reference voltage monitoring circuit is connected to the buffering inverter so as to minimize an effect of a variation in the value of the reference voltage on signal propagation delay times. The buffer circuit can further include a driver circuit with a comparator. A method of managing signal propagation delays includes providing a differential amplifier, providing at least one buffering inverter, and providing a reference voltage monitoring circuit. The reference voltage monitoring circuit can maintain signal propagation delays as a reference voltage varies.
    • 缓冲电路包括差分放大器,缓冲反相器和参考电压监视电路。 差分放大器具有参考电压和电流源作为输入。 缓冲反相器具有差分放大器的输出作为输入。 参考电压监视电路包括两个晶体管和一个第二电流源。 参考电压监视电路的输出端连接到缓冲反相器,以便最小化参考电压值对信号传播延迟时间的影响。 缓冲电路还可以包括具有比较器的驱动电路。 管理信号传播延迟的方法包括提供差分放大器,提供至少一个缓冲反相器,以及提供参考电压监视电路。 参考电压监视电路可以在参考电压变化时保持信号传播延迟。
    • 44. 发明申请
    • Input buffer circuit including reference voltage monitoring circuit
    • 输入缓冲电路,包括参考电压监控电路
    • US20050134331A1
    • 2005-06-23
    • US10739097
    • 2003-12-19
    • Jung KimJonghee Han
    • Jung KimJonghee Han
    • H03B1/00H03K19/003H03K19/0185
    • H03K19/00384H03K19/018528
    • A buffer circuit includes a differential amplifier, a buffering inverter, and a reference voltage monitoring circuit. The differential amplifier has a reference voltage and a current source as inputs. The buffering inverter has an output of the differential amplifier as an input. The reference voltage monitoring circuit includes two transistors and a second current source. An output of the reference voltage monitoring circuit is connected to the buffering inverter so as to minimize an effect of a variation in the value of the reference voltage on signal propagation delay times. The buffer circuit can further include a driver circuit with a comparator. A method of managing signal propagation delays includes providing a differential amplifier, providing at least one buffering inverter, and providing a reference voltage monitoring circuit. The reference voltage monitoring circuit can maintain signal propagation delays as a reference voltage varies.
    • 缓冲电路包括差分放大器,缓冲反相器和参考电压监视电路。 差分放大器具有参考电压和电流源作为输入。 缓冲反相器具有差分放大器的输出作为输入。 参考电压监视电路包括两个晶体管和一个第二电流源。 参考电压监视电路的输出端连接到缓冲反相器,以便最小化参考电压值对信号传播延迟时间的影响。 缓冲电路还可以包括具有比较器的驱动电路。 管理信号传播延迟的方法包括提供差分放大器,提供至少一个缓冲反相器,以及提供参考电压监视电路。 参考电压监视电路可以在参考电压变化时保持信号传播延迟。
    • 45. 发明授权
    • Input buffer with differential amplifier
    • 带差分放大器的输入缓冲器
    • US06891763B1
    • 2005-05-10
    • US10744804
    • 2003-12-23
    • Jonghee Han
    • Jonghee Han
    • G11C7/10G11C11/4093G11C7/00
    • G11C7/1084G11C7/1066G11C7/1078G11C11/4093
    • Embodiments of the present invention are illustrated in a random access memory. In one embodiment, a random access memory comprises an array of memory cells, a write circuit, and an input buffer configured to receive data and pass the received data to the write circuit that writes the received data into the array of memory cells. The input buffer comprises a differential amplifier configured to receive the data and in response to the received data supply a first signal and a second signal that is the compliment of the first signal. The input buffer also comprises a first transistor configured to be controlled by the first signal and a second transistor configured to be controlled by the second signal. The first transistor and the second transistor are turned on to provide a current path through the first transistor and the second transistor to change the first signal in response to a transition in the received data.
    • 本发明的实施例在随机存取存储器中示出。 在一个实施例中,随机存取存储器包括存储器单元阵列,写入电路和输入缓冲器,其被配置为接收数据并将接收到的数据传递到将所接收的数据写入存储器单元阵列的写入电路。 输入缓冲器包括差分放大器,其被配置为接收数据并且响应于接收到的数据提供第一信号和作为第一信号的补充的第二信号。 输入缓冲器还包括被配置为由第一信号控制的第一晶体管和被配置为由第二信号控制的第二晶体管。 第一晶体管和第二晶体管导通以提供通过第一晶体管和第二晶体管的电流路径,以响应于接收数据中的转变来改变第一信号。
    • 48. 发明授权
    • High resolution interleaved delay chain
    • 高分辨率交错延迟链
    • US06774691B2
    • 2004-08-10
    • US10337606
    • 2003-01-07
    • Jonghee HanJung Pill Kim
    • Jonghee HanJung Pill Kim
    • H03L706
    • H03L7/0814H03K5/133H03K2005/00058
    • An improved delay chain for use in a delay locked loop which provides smooth phase adjustment and high resolution. In a delay chain having a series of cascaded unit delay elements, the outputs of a pair of contiguous delay elements (N, N+1) are selected for input to a phase blender. A coarse delay adjustment is carried out by selecting the outputs of the next pair of contiguous delay elements (N+1, N+2) and thus affects only one of the phase blender inputs. The phase blender provides a fine delay adjustment by generating an output whose phase is a weighted combination of the inputs, the weights having an inverse relationship. A coarse delay adjustment which affects an input of the phase blender is carried out when the weighting of that input is zero. Fine-to-coarse hand-over problems which characterize known delay locked loops are thus avoided.
    • 用于延迟锁定环的改进的延迟链,其提供平滑的相位调整和高分辨率。 在具有一系列级联单元延迟元件的延迟链中,选择一对连续延迟元件(N,N + 1)的输出用于输入到相位混合器。 通过选择下一对连续延迟元件(N + 1,N + 2)的输出来执行粗略延迟调整,因此仅影响一个相位搅拌器输入。 相位混合器通过产生其相位是输入的加权组合的输出来提供精细的延迟调整,权重具有反比关系。 当该输入的加权为零时,执行影响相位混合器的输入的粗略延迟调整。 因此避免了表征已知延迟锁定环的细到粗移交问题。