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41. 发明授权

US5879982A Methods of forming integrated circuit memory devices having improved electrical interconnects therein 失效
标题翻译：形成其中具有改进的电互连的集成电路存储器件的方法
公开(公告)号：US5879982A
公开(公告)日：1999-03-09
申请号：US948566
申请日：1997-10-10
申请人： In-sun Park , Byung-hee Kim , Se-jun Oh , Sang-min Lee
发明人： In-sun Park , Byung-hee Kim , Se-jun Oh , Sang-min Lee
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/8239 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792
CPC分类号： H01L27/10844 , H01L27/1052 , H01L27/10852
摘要： Methods of forming integrated circuit memory devices include the steps of forming a first electrically insulating layer on a semiconductor substrate containing memory cells in a memory cell array region and peripheral circuits for driving the memory cells in a peripheral circuit region adjacent the memory cell array region. An etch-stopping layer is then formed on the first electrically insulating layer and then steps are performed to form a first electrically conductive layer on the etch-stopping layer, form a ferroelectric layer on the first electrically conductive layer, form a second electrode layer on the ferroelectric layer, etch the second electrode layer and ferroelectric layer in sequence using a first mask to define a second electrode and then etch the first electrically conductive layer using a second mask to simultaneously define a first electrode and a first interconnection layer comprising the same material. A second electrically insulating layer is then formed on the second electrode and first interconnection layer. First and second vias are then formed in the second electrically insulating layer, to expose the second electrode and first interconnection layer, respectively. A second electrically conductive layer is then patterned in the first and second vias.
摘要翻译：形成集成电路存储器件的方法包括以下步骤：在包含存储单元阵列区域中的存储单元的半导体衬底上形成第一电绝缘层，以及用于驱动与存储单元阵列区域相邻的外围电路区域中的存储单元的外围电路。然后在第一电绝缘层上形成蚀刻停止层，然后执行步骤以在蚀刻停止层上形成第一导电层，在第一导电层上形成铁电层，形成第二电极层铁电层，使用第一掩模依次蚀刻第二电极层和铁电层以限定第二电极，然后使用第二掩模蚀刻第一导电层，以同时限定第一电极和包含相同材料的第一互连层。然后在第二电极和第一互连层上形成第二电绝缘层。然后在第二电绝缘层中形成第一和第二通孔，以分别露出第二电极和第一互连层。然后在第一和第二通孔中将第二导电层图案化。

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