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41. 发明授权

US07664891B2 Modular data transfer architecture 有权
标题翻译：模块化数据传输架构
公开(公告)号：US07664891B2
公开(公告)日：2010-02-16
申请号：US11005926
申请日：2004-12-06
申请人： Varghese George
发明人： Varghese George
IPC分类号： G06F13/00
CPC分类号： G06F15/7825
摘要： A system on chip (SoC) integrated circuit includes a plurality of computational blocks. A modular data transfer architecture interconnects the computational blocks for intra-chip communications. The computational blocks include an initiator block and a target block, with the initiator block originating a data communication having a global address associated with the target block. The modular data transfer architecture includes a first peripheral module having an initiator port connected to the initiator block to receive the data communication and a second peripheral module having a target port connected to the target block. A first port mapper within the first peripheral module maps the global address to a first peripheral module target port along a data path towards the second peripheral module. A second port mapper within the second peripheral module maps the global address to the target port connected to the target block. The modular data transfer architecture further includes a plurality of internal modules support intra-chip communications. Each internal module has a plurality of initiator ports connected to target ports of other modules and a plurality of target ports connected to initiator ports of other modules. An internal port mapper for each internal module maps the global address to a certain internal module target port along the data path towards the second peripheral module.
摘要翻译：片上系统（SoC）集成电路包括多个计算块。模块化数据传输架构将用于片内通信的计算块互连。计算块包括发起者块和目标块，其中发起者块发起具有与目标块相关联的全局地址的数据通信。模块化数据传输架构包括第一外围模块，其具有连接到启动器块的发起端口以接收数据通信，以及具有连接到目标块的目标端口的第二外围模块。第一外围模块内的第一端口映射器将全局地址映射到沿第二外围模块的数据路径的第一外围模块目标端口。第二个外围模块中的第二个端口映射器将全局地址映射到连接到目标块的目标端口。模块化数据传输架构还包括多个内部模块支持片上通信。每个内部模块具有连接到其他模块的目标端口的多个启动器端口和连接到其他模块的启动器端口的多个目标端口。每个内部模块的内部端口映射器将全局地址映射到沿着数据路径的某个内部模块目标端口朝向第二个外围模块。

42. 发明申请

US20090199024A1 METHOD, APPARATUS AND SYSTEM TO DYNAMICALLY CHOOSE AN AOPTIMUM POWER STATE 有权
标题翻译：方法，装置和动态动态选择系统
公开(公告)号：US20090199024A1
公开(公告)日：2009-08-06
申请号：US12419855
申请日：2009-04-07
申请人： Sanjeev Jahagirdar , Varghese George , Jose Allarey , Eric Heit
发明人： Sanjeev Jahagirdar , Varghese George , Jose Allarey , Eric Heit
IPC分类号： G06F1/00
CPC分类号： G06F1/3203
摘要： Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described.
摘要翻译：本发明的一些实施例包括用于动态选择最佳功率状态的装置和方法。在一些实施例中，最佳功率状态可以根据关于各种功率状态的历史信息来确定，该装置或装置的任何实施例装备有该方法的装置或操作实施例的实施例可能会遇到。一些实施例可以生成寄存器来维护关于各种功率状态的信息。在一些实施例中，功率管理逻辑可以基于该信息来确定最佳功率状态。描述其他实施例。

43. 发明申请

US20080215875A1 Method and apparatus for establishing safe processor operating points 有权
标题翻译：建立安全处理器工作点的方法和装置
公开(公告)号：US20080215875A1
公开(公告)日：2008-09-04
申请号：US12081204
申请日：2008-04-11
申请人： Stephen Anthony Fischer , Varghese George , Sanjeev Jahagirdar , Stephen H. Gunther
发明人： Stephen Anthony Fischer , Varghese George , Sanjeev Jahagirdar , Stephen H. Gunther
IPC分类号： G06F1/08 , G06F1/24
CPC分类号： G06F21/57 , G06F1/324 , G06F1/3296 , G06F21/575 , G06F21/70 , G06F21/81 , G06F2221/2101 , Y02D10/126
摘要： A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.
摘要翻译：提供了一种用于建立安全处理器工作点的系统和方法。一些实施例可以包括防篡改存储元件，其存储关于可调节处理器操作参数的一个或多个操作点的信息。一些实施例可以进一步包括用于确定当前处理器工作点是操作参数的元件，以及将操作参数的当前操作点与存储的信息进行比较的元件。

44. 发明授权

US07290155B2 Method, system, and apparatus for dynamically configuring the operating point utilized for thermal management of an integrated circuit 有权
标题翻译：用于动态地配置用于集成电路的热管理的工作点的方法，系统和装置
公开(公告)号：US07290155B2
公开(公告)日：2007-10-30
申请号：US10696469
申请日：2003-10-28
申请人： Varghese George , Stephen H. Gunther , Sanjeev Jahagirdar , Inder Sodhi
发明人： Varghese George , Stephen H. Gunther , Sanjeev Jahagirdar , Inder Sodhi
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/206 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172
摘要： Methods and circuits to define a thermal operating mode for a integrated device by defining an operating voltage and a frequency range.
摘要翻译：通过定义工作电压和频率范围来定义集成器件的热操作模式的方法和电路。

45. 发明授权

US07266712B2 Method, system, and apparatus for dynamically configuring the operating point utilized for thermal management of an integrated circuit 有权
公开(公告)号：US07266712B2
公开(公告)日：2007-09-04
申请号：US11521649
申请日：2006-09-15
申请人： Varghese George , Stephen H. Gunther , Sanjeev Jahagirdar , Inder Sodhi
发明人： Varghese George , Stephen H. Gunther , Sanjeev Jahagirdar , Inder Sodhi
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/206 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172
摘要： Methods and circuits to define a thermal operating mode for a integrated device by defining an operating voltage and a frequency range.

46. 发明申请

US20070157036A1 Method and apparatus for a zero voltage processor sleep state 有权
标题翻译：零电压处理器睡眠状态的方法和装置
公开(公告)号：US20070157036A1
公开(公告)日：2007-07-05
申请号：US11323254
申请日：2005-12-30
申请人： Sanjeev Jahagirdar , Varghese George , John Conrad , Robert Milstrey , Stephen Fischer , Alon Navch , Shai Rotem
发明人： Sanjeev Jahagirdar , Varghese George , John Conrad , Robert Milstrey , Stephen Fischer , Alon Navch , Shai Rotem
IPC分类号： G06F1/26
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
摘要： Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
摘要翻译：本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。处理器可以包括专用高速缓存存储器。电压调节器可以耦合到处理器以向处理器提供工作电压。在处理器转换到零电压电源管理状态期间，电压调节器施加到处理器的工作电压可以减小到大约零，并且与处理器相关联的状态变量可以被保存到专用高速缓冲存储器。

47. 发明申请

US20070150653A1 Processing of cacheable streaming data 审中-公开
标题翻译：可缓存流数据的处理
公开(公告)号：US20070150653A1
公开(公告)日：2007-06-28
申请号：US11315853
申请日：2005-12-22
申请人： Niranjan Cooray , Jack Doweck , Mark Buxton , Varghese George
发明人： Niranjan Cooray , Jack Doweck , Mark Buxton , Varghese George
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0831 , G06F12/0859
摘要： According to one embodiment of the invention, a method is disclosed for receiving a request for cacheable memory type data in a cache-controller in communication with a first cache memory; obtaining the requested data from a first memory device in communication with the first cache memory if the requested data does not resides in at least one of the cache-controller and the first cache memory; allocating a data storage buffer in the cache-controller for storage of the obtained data; and setting the allocated data storage buffer to a streaming data mode if the obtained data is a streaming data to prevent an unrestricted placement of the obtained streaming data into the first cache memory.
摘要翻译：根据本发明的一个实施例，公开了一种用于在与第一高速缓存存储器通信的高速缓存控制器中接收对可缓存存储器类型数据的请求的方法; 如果所请求的数据不驻留在所述高速缓存控制器和所述第一高速缓冲存储器中的至少一个中，则从与所述第一高速缓存存储器通信的第一存储器设备获得所请求的数据; 在所述高速缓存控制器中分配数据存储缓冲器以存储所获得的数据; 以及如果所获得的数据是流数据，则将所分配的数据存储缓冲器设置为流数据模式，以防止所获得的流数据被无限制地放置到第一高速缓冲存储器中。

48. 发明授权

US07210054B2 Maintaining processor execution during frequency transitioning 有权
标题翻译：在频率转换期间维护处理器执行
公开(公告)号：US07210054B2
公开(公告)日：2007-04-24
申请号：US10180836
申请日：2002-06-25
申请人： Sanjeev Jahagirdar , Islam Derhalli , Varghese George , Kedar Mangrulkar , Mathew Nazareth
发明人： Sanjeev Jahagirdar , Islam Derhalli , Varghese George , Kedar Mangrulkar , Mathew Nazareth
IPC分类号： G06F1/04
CPC分类号： G06F1/08
摘要： An embodiment of the present invention includes a standby clock generator and a selector. The standby clock generator generates a standby clock synchronous to a core clock. The core clock is generated by a core clock generator during a normal operation mode. The core clock generator stops the core clock during a frequency transition. The selector generates a processor clock from the standby clock during the frequency transition from the normal operation mode according to a selector control signal.
摘要翻译：本发明的实施例包括备用时钟发生器和选择器。备用时钟发生器产生与内核时钟同步的备用时钟。内核时钟由正常操作模式下的核心时钟发生器产生。核心时钟发生器在频率转换期间停止核心时钟。根据选择器控制信号，从正常操作模式的频率转换期间，选择器从待机时钟产生处理器时钟。

49. 发明授权

US07205793B2 Self-programmable bidirectional buffer circuit and method 有权
标题翻译：自编程双向缓冲电路及方法
公开(公告)号：US07205793B2
公开(公告)日：2007-04-17
申请号：US11393934
申请日：2006-03-30
申请人： Varghese George
发明人： Varghese George
IPC分类号： H03K19/0175
CPC分类号： H03K19/01759
摘要： The present invention is directed to programmable bidirectional buffers and methods for programming such buffers. One method of according to an aspect of the present invention is a method of configuring a bidirectional buffer including first and second signal nodes. The method includes applying a configuration signal on one of the first and second signal nodes and configuring the buffer responsive to the applied configuration signal.
摘要翻译：本发明涉及用于编程这种缓冲器的可编程双向缓冲器和方法。根据本发明的一个方面的一种方法是配置包括第一和第二信号节点的双向缓冲器的方法。该方法包括在第一和第二信号节点之一上应用配置信号并且响应于所应用的配置信号来配置缓冲器。

50. 发明申请

US20070011477A1 Method, system, and apparatus for dynamically configuring the operating point utilized for thermal management of an integrated circuit 有权
公开(公告)号：US20070011477A1
公开(公告)日：2007-01-11
申请号：US11521649
申请日：2006-09-15
申请人： Varghese George , Stephen Gunther , Sanjeev Jahagirdar , Inder Sodhi
发明人： Varghese George , Stephen Gunther , Sanjeev Jahagirdar , Inder Sodhi
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/206 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172
摘要： Methods and circuits to define a thermal operating mode for a integrated device by defining an operating voltage and a frequency range.

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