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41. 发明申请

US20080025109A1 SRAM device and operating method 有权
公开(公告)号：US20080025109A1
公开(公告)日：2008-01-31
申请号：US11493345
申请日：2006-07-26
申请人： Cheng Hung Lee
发明人： Cheng Hung Lee
IPC分类号： G11C7/10
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , H01L2924/0002 , H01L2924/00
摘要： An improved SRAM cell and its operating method are disclosed. The SRAM cell comprises at least four original transistors, e.g., a pair of pass-gate transistors and a pair of pull-up transistors. The SRAM cell also comprises a pair of parasitic transistors formed by making contacts to a Pwell underneath a buried insulation layer to make the Pwell a gate terminal; hence the buried insulation layer serves as a gate insulation for the parasitic transistor.

42. 发明授权

US08982609B2 Memory having read assist device and method of operating the same 有权
标题翻译：具有读取辅助装置的存储器及其操作方法
公开(公告)号：US08982609B2
公开(公告)日：2015-03-17
申请号：US13372099
申请日：2012-02-13
申请人： Jung-Ping Yang , Hong-Chen Cheng , Chih-Chieh Chiu , Chia-En Huang , Cheng Hung Lee
发明人： Jung-Ping Yang , Hong-Chen Cheng , Chih-Chieh Chiu , Chia-En Huang , Cheng Hung Lee
IPC分类号： G11C11/00
CPC分类号： G11C11/4094 , G11C11/419
摘要： A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first voltage on the first bit line toward a predetermined voltage in response to a first datum being read out from the memory cell. The read assist device includes a first circuit configured to establish a first current path between the first bit line and a node of the predetermined voltage during a first stage. The read assist device further includes a second circuit configured to establish a second current path between the first bit line and the node of the predetermined voltage during a second, subsequent stage.
摘要翻译：存储器包括第一位线，耦合到第一位线的存储器单元和耦合到第一位线的读取辅助器件。读取辅助装置被配置为响应于从存储器单元读出的第一数据，将第一位线上的第一电压拉向预定电压。读取辅助装置包括第一电路，其被配置为在第一阶段期间在第一位线和预定电压的节点之间建立第一电流路径。读取辅助装置还包括第二电路，其被配置为在第二后续阶段期间在第一位线和预定电压的节点之间建立第二电流路径。

43. 发明授权

US08634268B2 Memory circuit having decoding circuits and method of operating the same 有权
标题翻译：具有解码电路的存储电路及其操作方法
公开(公告)号：US08634268B2
公开(公告)日：2014-01-21
申请号：US12912971
申请日：2010-10-27
申请人： Cheng Hung Lee , Hsu-Shun Chen
发明人： Cheng Hung Lee , Hsu-Shun Chen
IPC分类号： G11C8/10
CPC分类号： G11C8/10 , G11C11/418
摘要： The present application discloses a memory circuit having a first decoder coupled to a first memory bank and configured to receive a plurality of address control signals and to generate a first plurality of cell selection signals responsive to the plurality of address control signals and a second decoder coupled to a second memory bank and configured to receive a plurality of inverted address control signals and to generate a second plurality of cell selection signals responsive to the plurality of inverted address control signals. The memory circuit also has an address control signal buffer coupled to the second decoder and configured to convert the plurality of address control signals into the plurality of inverted address control signals.
摘要翻译：本申请公开了一种存储器电路，其具有耦合到第一存储体并被配置为接收多个地址控制信号并且响应于多个地址控制信号产生第一多个小区选择信号的第一解码器，耦合到第二存储体并且被配置为接收多个反相地址控制信号，并响应于所述多个反相地址控制信号产生第二多个单元选择信号。存储器电路还具有耦合到第二解码器的地址控制信号缓冲器，并且被配置为将多个地址控制信号转换成多个反相地址控制信号。

44. 发明授权

US08519444B2 Modified design rules to improve device performance 有权
标题翻译：改进设计规则以提高设备性能
公开(公告)号：US08519444B2
公开(公告)日：2013-08-27
申请号：US12879447
申请日：2010-09-10
申请人： Annie Lum , Derek C. Tao , Cheng Hung Lee , Chung-Ji Lu , Hong-Chen Cheng , Vineet Kumar Agrawal , Keun-Young Kim , Pyong Yun Cho
发明人： Annie Lum , Derek C. Tao , Cheng Hung Lee , Chung-Ji Lu , Hong-Chen Cheng , Vineet Kumar Agrawal , Keun-Young Kim , Pyong Yun Cho
IPC分类号： H01L27/118
CPC分类号： G06F17/5068 , G06F17/5081 , G06F2217/12 , H01L27/0207 , H01L27/088 , Y02P90/265
摘要： The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.
摘要翻译：上述布局，装置结构和方法利用虚设装置将边缘结构和/或非允许结构的扩散区域扩展到虚设装置。这种扩散区域的扩展可解决或减少LOD和边缘效应问题。此外，在边缘装置旁边处理伪装置的栅极结构也仅允许在虚设装置旁边添加一个虚拟结构，并将该不动产保存在半导体芯片上。虚拟设备被禁用，其性能不重要。因此，利用虚设装置根据设计规则扩展边缘结构和/或非允许结构的扩散区域允许分辨率或降低或LOD和边缘效应发生，而不会降低成品率或增加布局面积。

45. 发明授权

US08385136B2 Memory circuit and method of operating the same 有权
标题翻译：存储电路及其操作方法
公开(公告)号：US08385136B2
公开(公告)日：2013-02-26
申请号：US12913087
申请日：2010-10-27
申请人： Cheng Hung Lee , Jung-Ping Yang
发明人： Cheng Hung Lee , Jung-Ping Yang
IPC分类号： G11C5/14
CPC分类号： G11C7/12 , G11C7/067
摘要： The present application discloses a memory circuit having a first data line configured to carry a first data line signal and a second data line configured to carry a second data line signal. Further, a first driver is coupled to the first data line and the second data line and configured to establish a first current path for the first data line responsive to the second data line signal. Similarly, a second driver is coupled to the first data line and the second data line and configured to establish a second current path for the second data line responsive to the first data line signal. The memory circuit further has a first driver enabling line configured to selectively enable the first driver and a second driver enabling line configured to selectively enable the second driver.
摘要翻译：本申请公开了一种具有配置成承载第一数据线信号的第一数据线和被配置为承载第二数据线信号的第二数据线的存储器电路。此外，第一驱动器耦合到第一数据线和第二数据线，并且被配置为响应于第二数据线信号建立用于第一数据线的第一电流路径。类似地，第二驱动器耦合到第一数据线和第二数据线，并且被配置为响应于第一数据线信号为第二数据线建立第二电流路径。存储器电路还具有第一驱动器使能线，其被配置为选择性地使第一驱动器和第二驱动器使能线被配置为选择性地启用第二驱动器。

46. 发明授权

US08279684B2 Method for extending word-line pulses 有权
标题翻译：扩展字线脉冲的方法
公开(公告)号：US08279684B2
公开(公告)日：2012-10-02
申请号：US12842189
申请日：2010-07-23
申请人： Hsu-Shun Chen , Cheng Hung Lee , Hong-Chen Cheng , Chung-Yi Wu
发明人： Hsu-Shun Chen , Cheng Hung Lee , Hong-Chen Cheng , Chung-Yi Wu
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C11/413
摘要： An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current.
摘要翻译：集成电路包括正电源节点，电流跟踪电路和包括并联耦合的多个电流路径的电流镜像电路。多个电流通路的电流反映了电流跟踪电路的电流。电流镜像电路被配置为响应于正电源节点上的正电源电压的减小而逐个关闭多个电流路径。集成电路还包括接收多个电流路径的求和电流的充电节点，其中充电节点上的电压被配置为通过对和电流的充电而增加。

47. 发明申请

US20120153433A1 Tuning the Efficiency in the Transmission of Radio-Frequency Signals Using Micro-Bumps 有权
标题翻译：调整使用微型轰击发射射频信号的效率
公开(公告)号：US20120153433A1
公开(公告)日：2012-06-21
申请号：US12974896
申请日：2010-12-21
申请人： Hsiao-Tsung Yen , Yu-Ling Lin , Cheng Hung Lee , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Cheng Hung Lee , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
IPC分类号： H01L23/552 , H01L23/00
CPC分类号： H01L23/60 , H01L23/66 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L27/0248 , H01L2223/6677 , H01L2224/0401 , H01L2224/05023 , H01L2224/05073 , H01L2224/05147 , H01L2224/05567 , H01L2224/05568 , H01L2224/05655 , H01L2224/13083 , H01L2224/13147 , H01L2224/13155 , H01L2224/14131 , H01L2224/16145 , H01L2224/16148 , H01L2224/16225 , H01L2224/16238 , H01L2224/17517 , H01L2224/81455 , H01L2225/06513 , H01L2924/00014 , H01L2924/01029 , H01L2924/13091 , H01L2924/14 , H01L2924/1421 , H01L2924/15192 , H01L2924/15311 , H01L2924/19104 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2224/131 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： A device includes a die including a main circuit and a first pad coupled to the main circuit. A work piece including a second pad is bonded to the die. A first plurality of micro-bumps is electrically coupled in series between the first and the second pads. Each of the plurality of micro-bumps includes a first end joining the die and a second end joining the work piece. A micro-bump is bonded to the die and the work piece. The second pad is electrically coupled to the micro-bump.
摘要翻译：一种器件包括：裸片，包括主电路和耦合到主电路的第一焊盘。包括第二垫的工件被结合到模具。第一多个微凸块在第一和第二焊盘之间串联电耦合。多个微型凸块中的每一个包括连接模具的第一端和连接工件的第二端。微凸块与模具和工件结合。第二焊盘电耦合到微凸起。

48. 发明申请

US20100315859A1 Eight-Transistor SRAM Memory with Shared Bit-Lines 有权
标题翻译：具有共享位线的八路晶体管SRAM存储器
公开(公告)号：US20100315859A1
公开(公告)日：2010-12-16
申请号：US12750430
申请日：2010-03-30
申请人： Cheng Hung Lee
发明人： Cheng Hung Lee
IPC分类号： G11C11/00 , G11C8/16
CPC分类号： G11C8/16 , G11C11/412
摘要： An integrated circuit structure includes a first static random access memory (SRAM) cell including a first read-port and a first write-port; and a second SRAM cell including a second read-port and a second write-port. The first SRAM cell and the second SRAM cell are in a same row and arranged along a row direction. A first word-line is coupled to the first SRAM cell. A second word-line is coupled to the second SRAM cell. A read bit-line is coupled to the first SRAM cell and the second SRAM cell, wherein the read bit-line extends in a column direction perpendicular to the row direction. A write bit-line is coupled to the first SRAM cell and the second SRAM cell.
摘要翻译：集成电路结构包括包括第一读取端口和第一写入端口的第一静态随机存取存储器（SRAM）单元; 以及包括第二读取端口和第二写入端口的第二SRAM单元。第一SRAM单元和第二SRAM单元位于同一行中并沿着行方向布置。第一字线耦合到第一SRAM单元。第二字线耦合到第二SRAM单元。读位线耦合到第一SRAM单元和第二SRAM单元，其中读位线在垂直于行方向的列方向上延伸。写位线耦合到第一SRAM单元和第二SRAM单元。

49. 发明申请

US20100230726A1 POWER LINE LAYOUT TECHNIQUES FOR INTEGRATED CIRCUITS HAVING MODULAR CELLS 有权
标题翻译：用于具有模块化电池的集成电路的功率线路布线技术
公开(公告)号：US20100230726A1
公开(公告)日：2010-09-16
申请号：US12786003
申请日：2010-05-24
申请人： Cheng Hung Lee
发明人： Cheng Hung Lee
IPC分类号： H01L27/10
CPC分类号： H01L27/0207 , H01L27/105
摘要： An integrated circuit (IC) chip includes a first memory cell array block having a first metal layer containing at least two power lines, and a second memory cell array block containing at least two power lines independent of each other, wherein all the power lines on the first metal layer serving the first memory cell array block do not extend into the second memory cell array block, and all the power lines on the first metal layer serving the second memory cell array block do not extend into the first memory cell array block.
摘要翻译：集成电路（IC）芯片包括具有包含至少两条电源线的第一金属层的第一存储单元阵列块和包含彼此独立的至少两条电源线的第二存储单元阵列块，其中所有电源线在服务于第一存储单元阵列块的第一金属层不延伸到第二存储单元阵列块中，并且服务于第二存储单元阵列块的第一金属层上的所有电力线不延伸到第一存储单元阵列块中。

50. 发明申请

US20100103719A1 Two-Stage 8T SRAM Cell Design 有权
标题翻译：两级8T SRAM单元设计
公开(公告)号：US20100103719A1
公开(公告)日：2010-04-29
申请号：US12259009
申请日：2008-10-27
申请人： Cheng Hung Lee
发明人： Cheng Hung Lee
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/412
摘要： An integrated circuit device includes a first word-line; a second word-line; a first bit-line; and a static random access memory (SRAM) cell. The SRAM cell includes a storage node; a pull-up transistor having a source/drain region coupled to the storage node; a pull-down transistor having a source/drain region coupled to the storage node; a first pass-gate transistor comprising a gate coupled to the first word-line; and a second pass-gate transistor including a gate coupled to the second word-line. Each of the first and the second pass-gate transistors includes a first source/drain region coupled to the first bit-line, and a second source/drain region coupled to the storage node.
摘要翻译：集成电路装置包括第一字线; 第二个字线; 第一个位线和静态随机存取存储器（SRAM）单元。 SRAM单元包括存储节点; 具有耦合到存储节点的源极/漏极区域的上拉晶体管; 具有耦合到存储节点的源极/漏极区域的下拉晶体管; 第一通过栅晶体管，包括耦合到第一字线的栅极; 以及包括耦合到第二字线的栅极的第二栅极晶体管。第一和第二栅极晶体管中的每一个包括耦合到第一位线的第一源极/漏极区域和耦合到存储节点的第二源极/漏极区域。

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