专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US09223580B2 Systems, methods and computer products for cross-thread scheduling 有权
标题翻译：用于跨线程调度的系统，方法和计算机产品
公开(公告)号：US09223580B2
公开(公告)日：2015-12-29
申请号：US11847556
申请日：2007-08-30
申请人： Alexandre E. Eichenberger , Michael K. Gschwind , John A Gunnels , James L. McInnes , Mark P. Mendell
发明人： Alexandre E. Eichenberger , Michael K. Gschwind , John A Gunnels , James L. McInnes , Mark P. Mendell
IPC分类号： G06F9/455 , G06F9/46 , G06F9/38 , G06F9/45
CPC分类号： G06F9/3851 , G06F8/445 , G06F9/3885
摘要： Systems, methods and computer products for cross-thread scheduling. Exemplary embodiments include a cross thread scheduling method for compiling code, the method including scheduling a scheduling unit with a scheduler sub-operation in response to the scheduling unit being in a non-multithreaded part of the code and scheduling the scheduling unit with a cross-thread scheduler sub-operation in response to the scheduling unit being in a multithreaded part of the code.
摘要翻译：用于跨线程调度的系统，方法和计算机产品。示例性实施例包括用于编译代码的交叉线程调度方法，所述方法包括：响应于所述调度单元处于所述代码的非多线程部分中的调度器子操作来调度调度单元，并且调度所述调度单元，响应于调度单元处于代码的多线程部分中的线程调度器子操作。

42. 发明授权

US09063759B2 Optimizing subroutine calls based on architecture level of called subroutine 有权
标题翻译：根据调用子程序的架构级别优化子程序调用
公开(公告)号：US09063759B2
公开(公告)日：2015-06-23
申请号：US13432393
申请日：2012-03-28
申请人： Michael K. Gschwind
发明人： Michael K. Gschwind
IPC分类号： G06F9/44 , G06F9/445
CPC分类号： G06F9/44521 , G06F9/4484
摘要： A technique is provided for generating stubs. A processing circuit receives a call to a called function. The processing circuit retrieves a called function property of the called function. The processing circuit generates a stub for the called function based on the called function property.
摘要翻译：提供了一种用于生成存根的技术。处理电路接收对被叫功能的呼叫。处理电路检索被叫函数的被叫函数属性。处理电路基于被叫函数特性生成被叫函数的存根。

43. 发明授权

US08904153B2 Vector loads with multiple vector elements from a same cache line in a scattered load operation 有权
标题翻译：在分散加载操作中，来自相同高速缓存行的多个向量元素的向量加载
公开(公告)号：US08904153B2
公开(公告)日：2014-12-02
申请号：US12876321
申请日：2010-09-07
申请人： Alexandre E. Eichenberger , Michael K. Gschwind , Valentina Salapura
发明人： Alexandre E. Eichenberger , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/345 , G06F9/30 , G06F9/38 , G06F15/80
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/3857 , G06F15/8069
摘要： Mechanisms for performing a scattered load operation are provided. With these mechanisms, an extended address is received in a cache memory of a processor. The extended address has a plurality of data element address portions that specify a plurality of data elements to be accessed using the single extended address. Each of the plurality of data element address portions is provided to corresponding data element selector logic units of the cache memory. Each data element selector logic unit in the cache memory selects a corresponding data element from a cache line buffer based on a corresponding data element address portion provided to the data element selector logic unit. Each data element selector logic unit outputs the corresponding data element for use by the processor.
摘要翻译：提供了执行分散加载操作的机构。利用这些机制，扩展地址被接收在处理器的高速缓冲存储器中。扩展地址具有多个数据元素地址部分，其指定使用单个扩展地址来访问的多个数据元素。多个数据元素地址部分中的每一个被提供给高速缓冲存储器的相应数据元素选择器逻辑单元。高速缓冲存储器中的每个数据元素选择器逻辑单元基于提供给数据元素选择器逻辑单元的相应数据元素地址部分从高速缓存行缓冲器中选择相应的数据元素。每个数据元素选择器逻辑单元输出相应的数据元素供处理器使用。

44. 发明申请

US20130262821A1 PERFORMING PREDECODE-TIME OPTIMIZED INSTRUCTIONS IN CONJUNCTION WITH PREDECODE TIME OPTIMIZED INSTRUCTION SEQUENCE CACHING 有权
标题翻译：与预定时间优化的指令序列缓存执行预定时间优化的指令
公开(公告)号：US20130262821A1
公开(公告)日：2013-10-03
申请号：US13432357
申请日：2012-03-28
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/382 , G06F9/3017 , G06F9/3808 , G06F9/384
摘要： A method for performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching. The method includes receiving a first instruction of an instruction sequence and a second instruction of the instruction sequence and determining if the first instruction and the second instruction can be optimized. In response to the determining that the first instruction and second instruction can be optimized, the method includes, preforming a pre-decode optimization on the instruction sequence and generating a new second instruction, wherein the new second instruction is not dependent on a target operand of the first instruction and storing a pre-decoded first instruction and a pre-decoded new second instruction in an instruction cache. In response to determining that the first instruction and second instruction can not be optimized, the method includes, storing the pre-decoded first instruction and a pre-decoded second instruction in the instruction cache.
摘要翻译：一种执行预解码时间优化指令并结合预解码时间优化指令序列缓存的方法。该方法包括接收指令序列的第一指令和指令序列的第二指令，并且确定是否可以优化第一指令和第二指令。响应于确定可以优化第一指令和第二指令，该方法包括：对指令序列执行预解码优化并产生新的第二指令，其中新的第二指令不依赖于目标操作数所述第一指令并将预解码的第一指令和预解码的新的第二指令存储在指令高速缓存中。响应于确定第一指令和第二指令不能被优化，该方法包括：将预解码的第一指令和预解码的第二指令存储在指令高速缓存中。

45. 发明申请

US20130212139A1 MIXED PRECISION ESTIMATE INSTRUCTION COMPUTING NARROW PRECISION RESULT FOR WIDE PRECISION INPUTS 有权
标题翻译：混合精度估计指标计算精度高精度结果进行精确输入
公开(公告)号：US20130212139A1
公开(公告)日：2013-08-15
申请号：US13369470
申请日：2012-02-09
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F7/483 , G06F7/499 , G06F17/10
CPC分类号： G06F7/483 , G06F7/499 , G06F7/49905
摘要： A technique is provided for performing a mixed precision estimate. A processing circuit receives an input of a first precision having a wide precision value. The processing circuit computes an output in an output exponent range corresponding to a narrow precision value based on the input having the wide precision value.
摘要翻译：提供了一种用于执行混合精度估计的技术。处理电路接收具有宽精度值的第一精度的输入。处理电路基于宽精度值的输入，计算与窄精度值对应的输出指数范围内的输出。

46. 发明申请

US20130086570A1 LINKING CODE FOR AN ENHANCED APPLICATION BINARY INTERFACE (ABI) WITH DECODE TIME INSTRUCTION OPTIMIZATION 失效
标题翻译：链接代码用于增强应用二进制接口（ABI）与解码时间指令优化
公开(公告)号：US20130086570A1
公开(公告)日：2013-04-04
申请号：US13251793
申请日：2011-10-03
申请人： Robert J. Blainey , Michael K. Gschwind , James L. McInnes , Michael R. Meissner , Steven J. Munroe
发明人： Robert J. Blainey , Michael K. Gschwind , James L. McInnes , Michael R. Meissner , Steven J. Munroe
IPC分类号： G06F9/44
CPC分类号： G06F8/54 , G06F9/3017 , G06F9/342
摘要： A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable or data. The identified code sequence is configured to perform a memory reference function or a memory address computation function. It is determined that the offset location is within a specified distance of the base address and that a replacement of the identified code sequence with a replacement code sequence will not alter program semantics. The identified code sequence in the object file is replaced with the replacement code sequence that includes a no-operation (NOP) instruction or having fewer instructions than the identified code sequence. Linked executable code is generated based on the object file and the linked executable code is emitted.
摘要翻译：在目标文件中标识由多个指令构成的代码序列并指定与基地址的偏移量。与基地址的偏移量对应于配置为存储变量或数据地址的存储器中的偏移位置。所识别的代码序列被配置为执行存储器引用功能或存储器地址计算功能。确定偏移位置在基地址的指定距离内，并且用替换代码序列替换所识别的代码序列将不会改变程序语义。目标文件中所识别的代码序列被替换为包含无操作（NOP）指令或具有比识别的代码序列少的指令的替换代码序列。链接的可执行代码是基于目标文件生成的，并且发送链接的可执行代码。

47. 发明申请

US20130086362A1 Managing a Register Cache Based on an Architected Computer Instruction Set Having Operand First-Use Information 有权
标题翻译：基于具有操作数首次使用信息的建筑计算机指令集管理寄存器缓存
公开(公告)号：US20130086362A1
公开(公告)日：2013-04-04
申请号：US13251426
申请日：2011-10-03
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/312
CPC分类号： G06F9/30145 , G06F9/30 , G06F9/30185 , G06F9/34 , G06F9/3826 , G06F9/384
摘要： A prefix instruction is executed and passes operands to a net instruction without storing the operands in an architected resource such that the execution of the next instruction uses the operands provided by the prefix instruction to perform an operation, the operands may be prefix instruction immediate field or a target register of the prefix instruction execution.
摘要翻译：执行前缀指令并将操作数传递到网络指令而不将操作数存储在架构资源中，使得下一条指令的执行使用由前缀指令提供的操作数来执行操作，操作数可以是前缀指令立即字段或前缀指令执行的目标寄存器。

48. 发明申请

US20130073836A1 FINE-GRAINED INSTRUCTION ENABLEMENT AT SUB-FUNCTION GRANULARITY 有权
公开(公告)号：US20130073836A1
公开(公告)日：2013-03-21
申请号：US13234785
申请日：2011-09-16
申请人： Michael K. Gschwind , Brett Olsson , Valentina Salapura
发明人： Michael K. Gschwind , Brett Olsson , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/302
CPC分类号： G06F9/3013 , G06F9/30025 , G06F9/30036 , G06F9/30098 , G06F9/30105 , G06F9/30112 , G06F9/3012 , G06F9/3016 , G06F9/30189
摘要： Fine-grained enablement at sub-function granularity. An instruction encapsulates different sub-functions of a function, in which the sub-functions use different sets of registers of a composite register file, and therefore, different sets of functional units. At least one operand of the instruction specifies which set of registers, and therefore, which set of functional units, is to be used in performing the sub-function. The instruction can perform various functions (e.g., move, load, etc.) and a sub-function of the function specifies the type of function (e.g., move-floating point; move-vector; etc.).

49. 发明授权

US08327344B2 Array reference safety analysis in the presence of loops with conditional control flow 失效
标题翻译：存在带有条件控制流的循环的阵列参考安全分析
公开(公告)号：US08327344B2
公开(公告)日：2012-12-04
申请号：US12250562
申请日：2008-10-14
申请人： Michael K. Gschwind
发明人： Michael K. Gschwind
IPC分类号： G06F9/45
CPC分类号： G06F8/4441
摘要： Mechanisms are provided for analyzing and optimizing loops with conditional control flow in source code based on array reference safety. Mechanisms are provided for analyzing blocks of the source code to identify a conditional control flow loop having loop source code specifying a total access range for an array reference. A safe access range, of the total access range of the array reference in the loop source code, is identified over which a compiler-based optimization of the loop source code can be safely applied without introducing new exception conditions. The compiler-based optimization of the loop source code is performed based on the identified safe access range to generate optimized code. The optimized code is output for generation of executable code for execution on a processor.
摘要翻译：提供了基于数组参考安全性的源代码中的条件控制流分析和优化循环机制。提供了用于分析源代码块的机制，以识别具有指定阵列引用的总访问范围的循环源代码的条件控制流程循环。确定循环源代码中数组引用的总访问范围的安全访问范围，可以在不引入新异常条件的情况下安全地应用循环源代码的基于编译器的优化。基于编译器的循环源代码的优化是基于识别的安全访问范围来执行的，以生成优化的代码。优化的代码被输出用于生成用于在处理器上执行的可执行代码。

50. 发明申请

US20120297373A1 METHODS FOR GENERATING CODE FOR AN ARCHITECTURE ENCODING AN EXTENDED REGISTER SPECIFICATION 审中-公开
公开(公告)号：US20120297373A1
公开(公告)日：2012-11-22
申请号：US13559274
申请日：2012-07-26
申请人： Michael K. Gschwind , Robert Kevin Montoye , Brett Olsson , John-David Wellman
发明人： Michael K. Gschwind , Robert Kevin Montoye , Brett Olsson , John-David Wellman
IPC分类号： G06F9/45
CPC分类号： G06F8/447
摘要： There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width instruction set includes identifying a non-contiguous register specifier. The method further includes generating a fixed-width instruction word that includes the non-contiguous register specifier.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式