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41. 发明授权

US6076157A Method and apparatus to force a thread switch in a multithreaded processor 失效
标题翻译：在多线程处理器中强制执行线程切换的方法和装置
公开(公告)号：US6076157A
公开(公告)日：2000-06-13
申请号：US956577
申请日：1997-10-23
申请人： John Michael Borkenhagen , Richard James Eickemeyer , William Thomas Flynn , Andrew Henry Wottreng
发明人： John Michael Borkenhagen , Richard James Eickemeyer , William Thomas Flynn , Andrew Henry Wottreng
IPC分类号： G06F9/38 , G06F9/48 , G06F9/44 , G06F9/24
CPC分类号： G06F9/4825 , G06F9/3851
摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.
摘要翻译：用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。每个线程根据执行状态在线程状态寄存器中具有相应的状态。线程开关逻辑包含一个线程开关控制寄存器，用于存储发生线程的条件。线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。线程开关逻辑还具有前进进程计数寄存器，以防止多线程处理器中的线程之间的重复线程切换。线程切换逻辑还响应于能够改变不同线程的优先级并从而取代线程切换事件的软件管理器。

42. 发明授权

US07844769B2 Computer system having an apportionable data bus and daisy chained memory chips 有权
标题翻译：具有可分配数据总线和菊花链存储器芯片的计算机系统
公开(公告)号：US07844769B2
公开(公告)日：2010-11-30
申请号：US11459955
申请日：2006-07-26
申请人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson
发明人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson
IPC分类号： G06F13/40 , G06F13/28
CPC分类号： G06F13/1678 , G06F13/1684
摘要： A memory system having a data bus coupling a memory controller and a memory. The data bus has a number of data bus bits. The data bus is programmably apportioned to a first portion dedicated to transmitting data from the memory controller to the memory and a second portion dedicated to transmitting data from the memory to the memory controller. The apportionment can be assigned by suitable connection of pins on a memory chip in the memory and the memory controller to logical values. Alternatively, the apportionment can be scanned into the memory controller and the memory at bring up time. In another alternative, the apportionment can be changed by suspending data transfer and dynamically changing the sizes of the first portion and the second portion.
摘要翻译：具有耦合存储器控制器和存储器的数据总线的存储器系统。数据总线具有多个数据总线位。数据总线可编程地分配给专用于从存储器控制器向存储器发送数据的第一部分和专用于将数据从存储器传送到存储器控制器的第二部分。分配可以通过将存储器中的存储器芯片上的引脚适当地连接到存储器控制器到逻辑值来分配。或者，可以在释放时间的情况下将分配扫描到存储器控制器和存储器中。在另一替代方案中，可以通过暂停数据传送并动态地改变第一部分和第二部分的大小来改变分配。

43. 发明授权

US07822936B2 Memory chip for high capacity memory subsystem supporting replication of command data 有权
标题翻译：支持高容量内存子系统的内存芯片支持复制命令数据
公开(公告)号：US07822936B2
公开(公告)日：2010-10-26
申请号：US11769001
申请日：2007-06-27
申请人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
发明人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
IPC分类号： G06F13/10
CPC分类号： G06F13/1684 , G06F12/084 , Y02D10/13 , Y02D10/14
摘要： A memory module contains a first interface for receiving data access commands and a second interface for re-transmitting data access commands to other memory modules, the second interface propagating multiple copies of received data access commands to multiple other memory modules. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports multiple replication of commands and another of which supports conventional daisy-chaining.
摘要翻译：存储器模块包括用于接收数据访问命令的第一接口和用于将数据访问命令重新传送到其他存储器模块的第二接口，第二接口将接收的数据访问命令的多个副本传播到多个其他存储器模块。存储器模块优选地用于以树形结构组织的高容量存储器子系统，其中数据访问是交错的。优选地，存储器模块具有多模式操作，其中之一支持命令的多个复制，另一个支持常规的菊花链。

44. 发明申请

US20100191894A1 Digital Data Architecture Employing Redundant Links in a Daisy Chain of Component Modules 有权
标题翻译：数字数据架构在组件模块的菊花链中使用冗余链路
公开(公告)号：US20100191894A1
公开(公告)日：2010-07-29
申请号：US12361666
申请日：2009-01-29
申请人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Philip Raymond Germann , William Paul Hovis , Mark Owen Maxson
发明人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Philip Raymond Germann , William Paul Hovis , Mark Owen Maxson
IPC分类号： G06F12/06
CPC分类号： G06F11/201 , G06F13/1684 , G11C5/06
摘要： A communications architecture utilizes modules arranged in a daisy-chain, each module supporting multiple input and output ports. Point-to-point links are arranged so that a first output link of each of multiple modules connects to the next module in the chain, and a second output link connects to a module after it, and inputs arranged similarly, so that any single module can be by-passed in the event of malfunction. Multiple chains may be cross-linked and/or serviced by hubs or chains of hubs. Preferably, the redundant links are used in a non-degraded operating mode to provide higher bandwidth and/or reduced latency of communication. The exemplary embodiment is a memory subsystem in which the modules are buffered memory chips.
摘要翻译：通信架构使用以菊花链布置的模块，每个模块支持多个输入和输出端口。点对点链路被布置成使得多个模块中的每一个的第一输出链路连接到链中的下一个模块，并且第二输出链路在其之后连接到模块，并且类似地布置输入，使得任何单个模块发生故障时可以旁路。多个链路可以由集线器或集线器的链路交联和/或服务。优选地，冗余链路以非降级操作模式使用，以提供更高的带宽和/或降低的通信延迟。示例性实施例是其中模块是缓冲存储器芯片的存储器子系统。

45. 发明申请

US20090300291A1 Implementing Cache Coherency and Reduced Latency Using Multiple Controllers for Memory System 审中-公开
标题翻译：使用多个控制器实现高速缓存一致性和减少延迟，用于内存系统
公开(公告)号：US20090300291A1
公开(公告)日：2009-12-03
申请号：US12132109
申请日：2008-06-03
申请人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , William Paul Hovis , Mark Owen Maxson
发明人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , William Paul Hovis , Mark Owen Maxson
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F13/1684
摘要： A method and apparatus implement cache coherency and reduced latency using multiple controllers for a memory system, and a design structure is provided on which the subject circuit resides. A first memory controller uses a first memory as its primary address space, for storage and fetches. A second memory controller is also connected to the first memory. A second memory controller uses a second memory as its primary address space, for storage and fetches. The first memory controller is also connected to the second memory. The first memory controller and the second memory controller, for example, are connected together by a processor communications bus. A request and send sequence of the invention sends data directly to a requesting memory controller eliminating the need to re-route data back through a responding controller, and improving the latency of the data transfer.
摘要翻译：一种方法和装置利用用于存储器系统的多个控制器来实现高速缓存一致性和减少的等待时间，并且提供主题电路所在的设计结构。第一个存储器控制器使用第一个存储器作为其主地址空间，用于存储和提取。第二存储器控制器也连接到第一存储器。第二个存储器控制器使用第二个存储器作为其主地址空间，用于存储和提取。第一存储器控制器也连接到第二存储器。例如，第一存储器控制器和第二存储器控制器通过处理器通信总线连接在一起。本发明的请求和发送顺序将数据直接发送到请求存储器控制器，消除了通过响应控制器重新路由数据的需要，并且改善了数据传输的延迟。

46. 发明授权

US07546410B2 Self timed memory chip having an apportionable data bus 失效
标题翻译：具有可分配数据总线的自定时存储芯片
公开(公告)号：US07546410B2
公开(公告)日：2009-06-09
申请号：US11459947
申请日：2006-07-26
申请人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson
发明人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/4243 , G06F13/4256
摘要： A self timed memory chip having an apportionable data bus. Access timing to an array on the memory chip is dynamically determined by circuitry on the memory chip. A ring oscillator on the memory chip has a frequency that is indicative of how fast an array on the memory chip can be accessed. The ring oscillator includes a bit line that is periodically charged and a memory element that subsequently discharges the bit line. The memory chip has a data bus interface having a number of bits. The data bus interface has a first number of bits apportioned to write data and a second number of bits apportioned to read data. The first number of bits and the second number of bits is programmable.
摘要翻译：具有可分配数据总线的自定时存储芯片。存储器芯片上的阵列的访问定时由存储器芯片上的电路动态地确定。存储器芯片上的环形振荡器具有表示可以访问存储器芯片上的阵列的速度的频率。环形振荡器包括周期性充电的位线和随后对位线进行放电的存储元件。该存储器芯片具有数位总线接口，该数据总线接口具有多个位。数据总线接口具有分配给写入数据的第一数量位和分配为读取数据的第二数量的位。第一位数和第二位数是可编程的。

47. 发明授权

US07533198B2 Memory controller and method for handling DMA operations during a page copy 失效
标题翻译：用于在页面复制期间处理DMA操作的存储器控制器和方法
公开(公告)号：US07533198B2
公开(公告)日：2009-05-12
申请号：US11246827
申请日：2005-10-07
申请人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Daniel Paul Kolz
发明人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Daniel Paul Kolz
IPC分类号： G06F13/28 , G06F12/00 , G06F13/00
CPC分类号： G06F13/28
摘要： A memory controller provides page copy logic that assures data coherency when a DMA operation to a page occurs during the copying of the page by the memory controller. The page copy logic compares the page index of the DMA operation to a copy address pointer that indicates the location currently being copied. If the page index of the DMA operation is less than the copy address pointer, the portion of the page that would be written to by the DMA operation has already been copied, so the DMA operation is performed to the physical address of the new page. If the page index of the DMA operation is greater than the copy address pointer, the portion of the page that would be written to by the DMA operation has not yet been copied, so the DMA operation is performed to the physical address of the old page.
摘要翻译：存储器控制器提供页面复制逻辑，以便在由存储器控制器复制页面期间在页面的DMA操作发生时确保数据一致性。页面复制逻辑将DMA操作的页面索引与指示当前正在复制的位置的复制地址指针进行比较。如果DMA操作的页面索引小于复制地址指针，则DMA操作将被写入的页面部分已被复制，因此DMA操作被执行到新页面的物理地址。如果DMA操作的页面索引大于复制地址指针，则DMA操作将被写入的页面部分尚未被复制，因此DMA操作被执行到旧页面的物理地址。

48. 发明授权

US07490186B2 Memory system having an apportionable data bus and daisy chained memory chips 有权
标题翻译：具有分配数据总线和菊花链存储器芯片的存储器系统
公开(公告)号：US07490186B2
公开(公告)日：2009-02-10
申请号：US11459959
申请日：2006-07-26
申请人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson
发明人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/1684
摘要： A memory system having a memory controller and a daisy chain of memory chips. The memory controller is coupled to memory chips in the daisy chain of memory chips by an address/command bus chain. The memory controller is coupled to memory chips in the daisy chain of memory chips by a data bus chain having a number of data bus bits. The data bus chain has a first portion of data bus bits dedicated to transmitting write data from the memory controller to a memory chip. The data bus chain has a second portion of data bus bits dedicated to transmitting read data from a memory chip to the memory controller. Apportionment of data bus bits between the first portion and the second portion is programmable. Programming is done by pin connection, scanning of a value, or by request from a processor coupled to the memory controller.
摘要翻译：一种具有存储器控制器和存储器芯片的菊花链的存储器系统。存储器控制器通过地址/命令总线链耦合到存储器芯片的菊花链中的存储器芯片。存储器控制器通过具有多个数据总线位的数据总线链耦合到存储器芯片的菊花链中的存储器芯片。数据总线链具有专用于从存储器控制器向存储器芯片发送写数据的数据总线位的第一部分。数据总线链具有专用于从存储器芯片向存储器控制器发送读取数据的数据总线位的第二部分。数据总线位在第一部分和第二部分之间的分配是可编程的。编程通过引脚连接，值的扫描，或者通过与存储器控制器耦合的处理器的请求来完成。

49. 发明申请

US20090006790A1 High Capacity Memory Subsystem Architecture Storing Interleaved Data for Reduced Bus Speed 有权
标题翻译：高容量存储器子系统架构存储用于减少总线速度的交错数据
公开(公告)号：US20090006790A1
公开(公告)日：2009-01-01
申请号：US11768995
申请日：2007-06-27
申请人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
发明人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
IPC分类号： G06F12/06
CPC分类号： G06F13/1684 , G06F13/1689
摘要： A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving
摘要翻译：高容量存储器子系统架构利用布置在一个或多个簇中的多个存储器模块，每个存储器模块连接到相应的集线器，该集线器又连接到存储器控制器。在集群内，数据被交织，以便每个数据访问命令访问集群的所有模块。集线器以较低的总线频率与存储器模块通信，但是在多个模块之间分配数据使集群能够保持存储器 - 控制器到集线器总线的复合数据速率。优选地，存储器系统采用具有双模操作的缓冲存储器芯片，其中之一支持数据被交错的集群配置，并且通信总线以减小的总线宽度和/或减小的总线频率进行操作以匹配交织电平

50. 发明申请

US20090006775A1 Dual-Mode Memory Chip for High Capacity Memory Subsystem 有权
标题翻译：用于大容量存储器子系统的双模存储芯片
公开(公告)号：US20090006775A1
公开(公告)日：2009-01-01
申请号：US11769011
申请日：2007-06-27
申请人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
发明人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G06F12/0607 , G06F13/1694 , Y02D10/13 , Y02D10/14
摘要： A dual-mode memory chip supports a first operation mode in which received data access commands contain chip select data to identify the chip addressed by the command, and control logic in the memory chip determines whether the command is addressed to the chip, and a second operation mode in which the received data access command addresses a set of multiple chips. Preferably, the first mode supports a daisy-chained configuration of memory chips. Preferably the second mode supports a hierarchical interleaved memory subsystem, in which each addressable set of chips is configured as a tree, command and write data being propagated down the tree, the number of chips increasing at each succeeding level of the tree.
摘要翻译：双模存储器芯片支持第一操作模式，其中接收的数据访问命令包含芯片选择数据以识别由命令寻址的芯片，并且存储器芯片中的控制逻辑确定命令是否寻址到芯片，第二操作模式操作模式，其中所接收的数据访问命令寻址一组多个芯片。优选地，第一模式支持存储芯片的菊花链配置。优选地，第二模式支持分层交错存储器子系统，其中每个可寻址的芯片集合被配置为树，命令和写入数据在树下传播，在树的每个后续级别增加的码片数量。

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