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41. 发明申请

US20100103952A1 Method, device, and system for data communication with preamble for reduced switching noise 有权
标题翻译：用于与前同步码进行数据通信以减少开关噪声的方法，设备和系统
公开(公告)号：US20100103952A1
公开(公告)日：2010-04-29
申请号：US12655624
申请日：2010-01-04
申请人： Seung-Jun Bae , Kwang-Chol Choe , Se-Won Seo
发明人： Seung-Jun Bae , Kwang-Chol Choe , Se-Won Seo
IPC分类号： H04L29/02
CPC分类号： H03M5/145
摘要： A data communication device or system includes a preamble unit and a data interface. The preamble unit generates or detects a first preamble having a first length for a first data line, and generates or detects a second preamble having a second length for a second data line. The first length is different from the second length, and data on the first and second data lines form parallel data. The data interface communicates a first data with the first preamble via the first data line and communicates a second data with the second preamble via the second data line. The respective length and/or respective pattern of each preamble are adjustable and/or programmable.
摘要翻译：数据通信设备或系统包括前同步码单元和数据接口。前导码单元产生或检测具有第一数据线的第一长度的第一前同步码，并且生成或检测第二数据线具有第二长度的第二前同步码。第一长度与第二长度不同，第一和第二数据线上的数据形成并行数据。所述数据接口经由所述第一数据线与所述第一前同步码传送第一数据，并经由所述第二数据线与所述第二前同步码传送第二数据。每个前导码的相应长度和/或相应模式是可调节的和/或可编程的。

42. 发明授权

US07541947B2 Semiconductor devices, a system including semiconductor devices and methods thereof 有权
公开(公告)号：US07541947B2
公开(公告)日：2009-06-02
申请号：US11802886
申请日：2007-05-25
申请人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Woo-Jin Lee
发明人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Woo-Jin Lee
IPC分类号： H03M7/00
CPC分类号： H03K19/00346 , H04L25/03866 , H04L25/14 , H04L25/4908
摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

43. 发明申请

US20090097339A1 Integrated Circuit Memory Devices Having Internal Command Generators Therein that Support Extended Command Sets Using Independent and Dependent Commands 有权
标题翻译：具有内部命令生成器的集成电路存储器件，其中支持使用独立和相关命令的扩展命令集
公开(公告)号：US20090097339A1
公开(公告)日：2009-04-16
申请号：US12236978
申请日：2008-09-24
申请人： Young-soo Sohn , Kwang-II Park , Seung-Jun Bae
发明人： Young-soo Sohn , Kwang-II Park , Seung-Jun Bae
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C11/4076 , G11C7/1006 , G11C7/1072 , G11C7/22 , G11C8/18
摘要： Integrated circuit memory devices include an internal command generator and a memory control circuit responsive to an internal command generated by the internal command generator. The internal command generator is configured to generate an internal command in response to a combination of an independent command and at least one dependent command received in sequence by the memory device. For example, the internal command generator may be configured to require the independent command to follow the at least one dependent command in the sequence when generating the internal command from the combination of the independent and dependent commands. Alternatively, the internal command generator may be configured to require the independent command to precede the at least one dependent command in the sequence before generating the internal command from the combination of the independent and dependent commands. These independent and dependent commands may be received by the memory device as respective multi-bit external command signals.
摘要翻译：集成电路存储器件包括响应于由内部命令发生器产生的内部命令的内部命令发生器和存储器控制电路。内部命令生成器被配置为响应于独立命令和由存储器装置依次接收的至少一个依赖命令的组合来生成内部命令。例如，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令时，要求独立命令遵循序列中的至少一个从属命令。或者，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令之前，要求独立命令在序列中的至少一个从属命令之前。这些独立和依赖的命令可以被存储器装置接收为相应的多位外部命令信号。

44. 发明授权

US07403040B2 Reference voltage generators for reducing and/or eliminating termination mismatch 有权
标题翻译：用于减少和/或消除终止失配的参考电压发生器
公开(公告)号：US07403040B2
公开(公告)日：2008-07-22
申请号：US11790014
申请日：2007-04-23
申请人： Kwang-Il Park , Seung-Jun Bae , Seong-Jin Jang
发明人： Kwang-Il Park , Seung-Jun Bae , Seong-Jin Jang
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： H03K19/017545
摘要： A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator.
摘要翻译：一种包括多个传输线的系统，向多个传输线中的每一个输出相应信号的发射机，经由各个传输线接收多个信号中的每一个的接收机，所述接收机包括连接到终端电压的连接路径，多个终端电路沿着连接路径分布，每个终端电路从连接路径接收唯一的终端电压，接收相应的信号并输出终止的输入信号;参考电压发生器，包括连接到公共电压的多个参考电压发生器单元，每个参考电压发生器单元独特地接收至少一个唯一的终端电压并输出参考电压，以及多个数据输入缓冲器，其接收相应的信号和从参考电压发生器输出的多个参考电压的适当参考电压。

45. 发明申请

US20080001626A1 Majority voter circuits and semiconductor devices including the same 有权
标题翻译：多数选民电路和半导体器件包括相同
公开(公告)号：US20080001626A1
公开(公告)日：2008-01-03
申请号：US11819600
申请日：2007-06-28
申请人： Seung-Jun Bae , Jeong-Don Lim , Gil-Shin Moon , Kwang-Il Park
发明人： Seung-Jun Bae , Jeong-Don Lim , Gil-Shin Moon , Kwang-Il Park
IPC分类号： H03K19/23
CPC分类号： H03K19/23
摘要： A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.
摘要翻译：多数选民电路被配置为基于第一输入数据和反相的第一输入数据生成选择信号。第一输入数据和反相的第一输入数据都包括奇数位，奇数位包括第一类型的位和第二类型的位。所生成的选择信号表示第一输入数据中的第一类型和第二类型的比特大多数。

46. 发明申请

US20070297552A1 Semiconductor device, a parallel interface system and methods thereof 有权
标题翻译：半导体器件，并行接口系统及其方法
公开(公告)号：US20070297552A1
公开(公告)日：2007-12-27
申请号：US11812438
申请日：2007-06-19
申请人： Seung-Jun Bae , Seong-Jin Jang , Beom-Sig Cho
发明人： Seung-Jun Bae , Seong-Jin Jang , Beom-Sig Cho
IPC分类号： H04L7/00
CPC分类号： G11C7/22 , H03K19/0966 , H04L7/0008 , H04L7/033 , H04L7/10
摘要： A semiconductor device, a parallel interface system and methods thereof are provided. The example semiconductor device may include a reference clock transmitting block generating a reference clock signal, a plurality of first transceiver blocks, each of the plurality of first transceiver blocks transmitting at least one parallel data bit signal based on one of a plurality of phase-controlled transmitting sampling clock signals and a per-pin deskew block controlling a phase of a transmitting sampling clock signal to generate the phase-controlled sampling clock signals for the respective plurality of transceiver blocks, the per-pin deskew block controlling the phase of each phase-controlled transmitting sampling clock signal based on a phase skew between a given training data bit signal, among a plurality of training data bit signals, corresponding to a given first transceiver block and the reference clock signal in a first operation mode, and based on phase skew information relating to a phase skew between a given parallel data bit signal of the at least one parallel data bit signal and the reference clock signal in a second operation mode. An example method may include reducing skew based on a comparison between a plurality of transmitted training data bit signals and a corresponding plurality of received training data bit signals in a first mode of operation and reducing skew based on received phase skew information relating to a phase skew difference between a reference signal and a parallel data bit signal in a second mode of operation.
摘要翻译：提供半导体器件，并行接口系统及其方法。示例性半导体器件可以包括产生参考时钟信号的参考时钟发送块，多个第一收发器块，多个第一收发器块中的每一个基于多个相位控制的多个第一收发器块中的一个发送至少一个并行数据位信号传输采样时钟信号和控制发射采样时钟信号的相位的每引脚偏移校正块，以产生相应的多个收发器模块的相位控制的采样时钟信号，每个引脚的去偏移块控制每个相位 - 基于相对于给定的第一收发器块的多个训练数据位信号中的给定训练数据位信号与第一操作模式中的参考时钟信号之间的相位偏移以及基于相位偏移的受控发送采样时钟信号与至少一个并行数据的给定并行数据位信号之间的相位偏移有关的信息在第二操作模式中的位信号和参考时钟信号。示例性方法可以包括基于在第一操作模式中的多个发送的训练数据比特信号与对应的多个接收的训练数据比特信号之间的比较来减少偏斜，并且基于接收到的相位偏移相关的相位偏移信息减少偏斜在第二操作模式中参考信号和并行数据位信号之间的差异。

47. 发明申请

US20060176988A1 Receiving apparatus and method thereof 有权
标题翻译：接收装置及其方法
公开(公告)号：US20060176988A1
公开(公告)日：2006-08-10
申请号：US11345451
申请日：2006-02-02
申请人： Young-Soo Sohn , Seung-Jun Bae , Hong-Jun Park , Jung-Hwan Choi
发明人： Young-Soo Sohn , Seung-Jun Bae , Hong-Jun Park , Jung-Hwan Choi
IPC分类号： H04B1/10
CPC分类号： H04L25/03038 , H04L7/0058
摘要： A receiving apparatus and method thereof. In an example, the receiving apparatus may include a clock generating unit generating a plurality of internal clock signals based on a received external clock signal and an equalization receiving unit receiving the plurality of internal clock signals and an input signal. The equalization receiving unit may determine an offset value and an equalization coefficient based on the plurality of internal clock signals and the input signal. The equalization receiving unit may adjust a received data signal based on the determined offset value and equalization coefficient.
摘要翻译：一种接收装置及其方法。在一个示例中，接收装置可以包括基于接收的外部时钟信号产生多个内部时钟信号的时钟产生单元和接收多个内部时钟信号的均衡接收单元和输入信号。均衡接收单元可以基于多个内部时钟信号和输入信号确定偏移值和均衡系数。均衡接收单元可以基于确定的偏移值和均衡系数来调整接收的数据信号。

48. 发明授权

US08395955B2 Semiconductor memory interface device with a noise cancellation circuit having a phase and gain adjustment circuitry 有权
标题翻译：具有噪声消除电路的半导体存储器接口装置具有相位和增益调整电路
公开(公告)号：US08395955B2
公开(公告)日：2013-03-12
申请号：US12948193
申请日：2010-11-17
申请人： Tae-Young Oh , Seung-Jun Bae , Kwnag-Il Park
发明人： Tae-Young Oh , Seung-Jun Bae , Kwnag-Il Park
IPC分类号： G11C7/02
CPC分类号： G11C7/10 , G11C7/02
摘要： A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line.
摘要翻译：提供了一种存储器接口电路，包括：第一信号输出电路，被配置为经由第一信号线将第一信号输出到第一I / O端子; 第二信号输出电路，被配置为经由第二信号线将第二信号输出到第二I / O端子; 以及噪声消除电路，其具有至少一个相位调整元件和至少一个增益调整元件，以减少由于在第一信号线上存在第一信号而在第二信号线上感应到的噪声信号，其中第二信号线是设置在第一信号线附近。

49. 发明授权

US08335291B2 Semiconductor device, a parallel interface system and methods thereof 有权
标题翻译：半导体器件，并行接口系统及其方法
公开(公告)号：US08335291B2
公开(公告)日：2012-12-18
申请号：US12929627
申请日：2011-02-04
申请人： Seung-Jun Bae , Seong-Jin Jang , Beom-Sig Cho
发明人： Seung-Jun Bae , Seong-Jin Jang , Beom-Sig Cho
IPC分类号： H04L7/00
CPC分类号： G11C7/22 , H03K19/0966 , H04L7/0008 , H04L7/033 , H04L7/10
摘要： A semiconductor device, a parallel interface system and methods thereof are provided. The example semiconductor device may include a reference clock transmitting block generating a reference clock signal, a plurality of first transceiver blocks, each of the plurality of first transceiver blocks transmitting at least one parallel data bit signal based on one of a plurality of phase-controlled transmitting sampling clock signals and a per-pin deskew block controlling a phase of a transmitting sampling clock signal to generate the phase-controlled sampling clock signals for the respective plurality of transceiver blocks, the per-pin deskew block controlling the phase of each phase-controlled transmitting sampling clock signal based on a phase skew between a given training data bit signal, among a plurality of training data bit signals, corresponding to a given first transceiver block and the reference clock signal in a first operation mode, and based on phase skew information relating to a phase skew between a given parallel data bit signal of the at least one parallel data bit signal and the reference clock signal in a second operation mode. An example method may include reducing skew based on a comparison between a plurality of transmitted training data bit signals and a corresponding plurality of received training data bit signals in a first mode of operation and reducing skew based on received phase skew information relating to a phase skew difference between a reference signal and a parallel data bit signal in a second mode of operation.
摘要翻译：提供半导体器件，并行接口系统及其方法。示例性半导体器件可以包括产生参考时钟信号的参考时钟发送块，多个第一收发器块，多个第一收发器块中的每一个基于多个相位控制的多个第一收发器块中的一个发送至少一个并行数据位信号传输采样时钟信号和控制发射采样时钟信号的相位的每引脚偏移校正块，以产生相应的多个收发器模块的相位控制的采样时钟信号，每个引脚的去偏移块控制每个相位 - 基于相对于给定的第一收发器块的多个训练数据位信号中的给定训练数据位信号与第一操作模式中的参考时钟信号之间的相位偏移以及基于相位偏移的受控发送采样时钟信号与至少一个并行数据的给定并行数据位信号之间的相位偏移有关的信息在第二操作模式中的位信号和参考时钟信号。示例性方法可以包括基于在第一操作模式中的多个发送的训练数据比特信号与对应的多个接收的训练数据比特信号之间的比较来减少偏斜，并且基于接收到的相位偏移相关的相位偏移信息减少偏斜在第二操作模式中参考信号和并行数据位信号之间的差异。

50. 发明申请

US20110298499A1 INTERNAL VOLTAGE GENERATOR AND INTEGRATED CIRCUIT DEVICE INCLUDING THE SAME 审中-公开
标题翻译：内部电压发生器和集成电路装置，包括它们
公开(公告)号：US20110298499A1
公开(公告)日：2011-12-08
申请号：US13110242
申请日：2011-05-18
申请人： Ho-Seok Seol , Seung-Jun Bae
发明人： Ho-Seok Seol , Seung-Jun Bae
IPC分类号： G05F3/16
CPC分类号： G11C5/147 , G11C11/4074
摘要： An internal voltage generator includes a comparison unit, a driving circuit and a bias unit. The comparison unit compares a reference voltage and an internal voltage and is configured to output a comparison voltage, which is based on a difference between the reference voltage and the internal voltage. The driving circuit receives the comparison voltage and an external power supply voltage and is configured to output the internal voltage to an output node in response to the comparison voltage. The bias unit receives the internal voltage and is configured to adaptively adjust a bias current that flows through the bias unit to drive the comparison unit, in consideration of a level of the internal voltage.
摘要翻译：内部电压发生器包括比较单元，驱动电路和偏置单元。比较单元比较参考电压和内部电压，并且被配置为输出基于参考电压和内部电压之间的差的比较电压。驱动电路接收比较电压和外部电源电压，并且被配置为响应于比较电压将内部电压输出到输出节点。偏置单元接收内部电压，并且被配置为考虑到内部电压的电平，自适应地调节流过偏置单元的偏置电流以驱动比较单元。

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