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41. 发明申请

US20080301377A1 DATA PROCESSING SYSTEM, CACHE SYSTEM AND METHOD FOR UPDATING AN INVALID COHERENCY STATE IN RESPONSE TO SNOOPING AN OPERATION 失效
标题翻译：数据处理系统，缓存系统和用于更新无效级别的方法以响应于操作
公开(公告)号：US20080301377A1
公开(公告)日：2008-12-04
申请号：US12190766
申请日：2008-08-13
申请人： GUY L. GUTHRIE , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
发明人： GUY L. GUTHRIE , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F2212/507
摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state that indicates that the address tag is valid and that the storage location does not contain valid data. In response to snooping an exclusive access operation, the exclusive access request specifying a target address matching the address tag and indicating a relative domain location of a requestor that initiated the exclusive access operation, the first cache memory updates the coherency state field from the first data-invalid coherency state to a second data-invalid coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, and whether a target memory block associated with the address tag is cached within the first coherency domain upon successful completion of the exclusive access operation based upon the relative location of the requestor.
摘要翻译：缓存相干数据处理系统至少包括第一和第二相干域。在数据处理系统的第一相关域内的第一高速缓冲存储器中，将与存储位置和地址标签相关联的一致性状态字段设置为指示地址标签有效的第一数据无效一致性状态，存储位置不包含有效数据。响应于窥探独占访问操作，所述专用访问请求指定与所述地址标签相匹配的目标地址并且指示发起所述独占访问操作的请求者的相对域位置，所述第一高速缓存存储器从所述第一数据更新所述一致性状态字段 - 无效的一致性状态到指示地址标签有效的第二数据无效一致性状态，存储位置不包含有效数据，以及与地址标签相关联的目标存储器块是否被缓存在第一相关域内基于请求者的相对位置成功完成独占访问操作。

42. 发明申请

US20080201533A1 REDUCING NUMBER OF REJECTED SNOOP REQUESTS BY EXTENDING TIME TO RESPOND TO SNOOP REQUEST 有权
标题翻译：通过延长时间减少违反SNOOP要求的数量以应对SNOOP要求
公开(公告)号：US20080201533A1
公开(公告)日：2008-08-21
申请号：US12114790
申请日：2008-05-04
申请人： Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is dispatched to a selector upon entering a bottom latch in the pipeline. The stall/reorder unit is not informed as to whether the dispatched snoop request is accepted by an arbitration mechanism for several clock cycles after the dispatch occurred. A copy of the dispatched snoop request is stored in a top latch in an overrun pipeline of latches in the first unit upon dispatching the snoop request. By maintaining information about the snoop request, the snoop request may be dispatched again to the selector in case the dispatched snoop request was rejected thereby increasing the chance that the snoop request will ultimately be accepted.
摘要翻译：用于减少拒绝的窥探请求数量的缓存，系统和方法。如果失速/重新排序单元未满，则在失速/重新排序单元中的锁存器管线中的第一可用锁存器中输入进入的窥探请求。输入的窥探请求在进入管道中的底部闩锁时被调度到选择器。失速/重新排序单元不知道发送后发送的几个时钟周期是否由仲裁机制接受发送的窥探请求。调度窥探请求的副本在调度窥探请求时被存储在第一单元中的锁存器的溢出管道中的顶部锁存器中。通过维护关于窥探请求的信息，可以在被发送的窥探请求被拒绝的情况下再次发送到选择器的窥探请求，从而增加窥探请求将最终被接受的机会。

43. 发明授权

US07386682B2 Reducing number of rejected snoop requests by extending time to respond to snoop request 有权
标题翻译：通过延长响应窥探请求的时间来减少被拒绝的窥探请求数
公开(公告)号：US07386682B2
公开(公告)日：2008-06-10
申请号：US11056764
申请日：2005-02-11
申请人： Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is dispatched to a selector upon entering a bottom latch in the pipeline. The stall/reorder unit is not informed as to whether the dispatched snoop request is accepted by an arbitration mechanism for several clock cycles after the dispatch occurred. A copy of the dispatched snoop request is stored in a top latch in an overrun pipeline of latches in the first unit upon dispatching the snoop request. By maintaining information about the snoop request, the snoop request may be dispatched again to the selector in case the dispatched snoop request was rejected thereby increasing the chance that the snoop request will ultimately be accepted.
摘要翻译：用于减少拒绝的窥探请求数量的缓存，系统和方法。如果失速/重新排序单元未满，则在失速/重新排序单元中的锁存器管线中的第一可用锁存器中输入进入的窥探请求。输入的窥探请求在进入管道中的底部闩锁时被调度到选择器。失速/重新排序单元不知道发送后发送的几个时钟周期是否由仲裁机制接受发送的窥探请求。调度窥探请求的副本在调度窥探请求时被存储在第一单元中的锁存器的溢出管道中的顶部锁存器中。通过维护关于窥探请求的信息，可以在被发送的窥探请求被拒绝的情况下再次发送到选择器的窥探请求，从而增加窥探请求将最终被接受的机会。

44. 发明申请

US20080120625A1 Data Processing System, Method and Interconnect Fabric that Protect Ownership Transfer with Non-Uniform Protection Windows 有权
标题翻译：数据处理系统，方法和互连结构，保护所有权转移与非均匀保护Windows
公开(公告)号：US20080120625A1
公开(公告)日：2008-05-22
申请号：US11560619
申请日：2006-11-16
申请人： Leo J. Clark , James S. Fields , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , James S. Fields , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F9/44
CPC分类号： G06F15/173
摘要： In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Latencies of requests and combined responses between the plurality of agents are observed. Each of the plurality of agents is configured with a respective duration of a protection window extension by reference to the observed latencies. Each protection window extension is a period following receipt of a combined response during winch an associated one of the plurality of agents protects transfer of coherency ownership of a data granule between agents. The plurality of agents employing protection window extensions in accordance with the configuration, and at least two of the agents have protection window extensions of differing durations.
摘要翻译：在数据处理系统中，多个代理之间进行通信。每个操作包括一个请求和组合的响应，代表对该请求的全系统响应。观察到请求的延迟和多个代理之间的组合响应。通过参考所观察到的延迟，多个代理中的每个被配置有保护窗口扩展的相应持续时间。每个保护窗口扩展是在绞盘期间接收到组合响应之后的周期，多个代理之一相关联的一个代理保护代理之间的数据粒子的一致性所有权的传送。多个代理根据配置使用保护窗口扩展，并且至少两个代理具有不同持续时间的保护窗口扩展。

45. 发明授权

US07340568B2 Reducing number of rejected snoop requests by extending time to respond to snoop request 失效
标题翻译：通过延长响应窥探请求的时间来减少被拒绝的窥探请求数
公开(公告)号：US07340568B2
公开(公告)日：2008-03-04
申请号：US11056740
申请日：2005-02-11
申请人： Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
发明人： Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.
摘要翻译：用于减少拒绝的窥探请求数量的缓存，系统和方法。缓存中的“停止/重新排序单元”从互连中接收窥探请求。窥探请求的诸如地址的信息被存储在失速/重新排序单元的队列中。停止/重新排序单元将窥探请求转发到也从处理器接收请求的选择器。仲裁机制选择来自处理器的窥探请求或请求。如果侦听请求被仲裁机制拒绝，关于窥探请求的信息（例如地址）可以被保留在停止/重新排序单元中。请求可能会稍后重新发送到选择器。该过程可以重复直到“n”个时钟周期。通过提供窥探请求仲裁机制接受的额外机会（n个时钟周期），最终可能会拒绝更少的侦听请求。

46. 发明授权

US06792521B2 Behavioral memory mechanism for a data processing system 失效
标题翻译：数据处理系统的行为记忆机制
公开(公告)号：US06792521B2
公开(公告)日：2004-09-14
申请号：US09978364
申请日：2001-10-16
申请人： Ravi K. Arimilli , William J. Starke
发明人： Ravi K. Arimilli , William J. Starke
IPC分类号： G06F1202
CPC分类号： G06F12/1054 , G06F12/109
摘要： A behavioral memory mechanism for a data processing system is disclosed. The data processing system includes a processor, a real memory, a behavioral address generator, and an address translator. The real memory has multiple real address locations, and each of the real address locations is associated with a corresponding one of many virtual address locations. The virtual address locations are divided into two non-overlapping regions, namely, an architecturally visible virtual memory region and a behavioral virtual memory region. The behavioral address generator generates a behavioral virtual memory address associated with the behavioral virtual memory region. The address translator translates the behavioral virtual memory address to a real address associated with the real memory.
摘要翻译：公开了一种用于数据处理系统的行为记忆机制。数据处理系统包括处理器，实际存储器，行为地址生成器和地址转换器。实际存储器具有多个实际地址位置，并且每个实际地址位置与许多虚拟地址位置中的对应的一个相关联。虚拟地址位置被分成两个非重叠区域，即，架构上可见的虚拟存储器区域和行为虚拟存储器区域。行为地址生成器生成与行为虚拟存储器区域相关联的行为虚拟存储器地址。地址转换器将行为虚拟存储器地址转换为与真实存储器相关联的真实地址。

47. 发明授权

US06785774B2 High performance symmetric multiprocessing systems via super-coherent data mechanisms 失效
标题翻译：通过超相干数据机制的高性能对称多处理系统
公开(公告)号：US06785774B2
公开(公告)日：2004-08-31
申请号：US09978362
申请日：2001-10-16
申请人： Ravi Kumar Arimilli , Guy Lynn Guthrie , William J. Starke , Derek Edward Williams
发明人： Ravi Kumar Arimilli , Guy Lynn Guthrie , William J. Starke , Derek Edward Williams
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A multiprocessor data processing system comprising a plurality of processing units, a plurality of caches, that is each affiliated with one of the processing units, and processing logic that, responsive to a receipt of a first system bus response to a coherency operation, causes the requesting processor to execute operations utilizing super-coherent data. The data processing system further includes logic eventually returning to coherent operations with other processing units responsive to an occurrence of a pre-determined condition. The coherency protocol of the data processing system includes a first coherency state that indicates that modification of data within a shared cache line of a second cache of a second processor has been snooped on a system bus of the data processing system. When the cache line is in the first coherency state, subsequent requests for the cache line is issued as a Z1 read on a system bus and one of two responses are received. If the response to the Z1 read indicates that the first processor should utilize local data currently available within the cache line, the first coherency state is changed to a second coherency state that indicates to the first processor that subsequent request for the cache line should utilize the data within the local cache and not be issued to the system interconnect. Coherency state transitions to the second coherency state is completed via the coherency protocol of the data processing system. Super-coherent data is provided to the processor from the cache line of the local cache whenever the second coherency state is set for the cache line and a request is received.
摘要翻译：一种多处理器数据处理系统，包括多个处理单元，多个高速缓存，每个高速缓存与每个处理单元中的一个相关联;以及处理逻辑，响应于对一致性操作的第一系统总线响应的接收，使得请求处理器使用超相干数据执行操作。数据处理系统还包括逻辑，其最终返回到响应于预定条件的发生的其他处理单元的相干操作。数据处理系统的一致性协议包括第一相关性状态，其指示在数据处理系统的系统总线上已经窥探第二处理器的第二高速缓存的共享高速缓存行内的数据的修改。当高速缓存行处于第一相关性状态时，在系统总线上作为Z1读取发出对高速缓存行的后续请求，并且接收到两个响应中的一个。如果对Z1读取的响应指示第一处理器应利用高速缓存行内当前可用的本地数据，则将第一相关性状态改变为第二相关性状态，其向第一处理器指示对高速缓存行的后续请求应当利用本地缓存内的数据，不发给系统互连。通过数据处理系统的一致性协议完成一致性状态转换到第二相关性状态。每当为高速缓存行设置第二相关性状态并接收到请求时，将超相干数据从本地高速缓存行提供给处理器。

48. 发明授权

US09110808B2 Formation of an exclusive ownership coherence state in a lower level cache upon replacement from an upper level cache of a cache line in a private shared owner state 有权
标题翻译：在私有共享所有者状态下从高速缓存行的高级缓存替换时，在下级缓存中形成独占所有权一致性状态
公开(公告)号：US09110808B2
公开(公告)日：2015-08-18
申请号：US12649725
申请日：2009-12-30
申请人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/00 , G06F12/08 , G06F9/38
CPC分类号： G06F12/0811 , G06F9/3834 , G06F12/0815 , G06F12/0831 , Y02D10/13
摘要： In response to a memory access request of a processor core that targets a target cache line, the lower level cache of a vertical cache hierarchy associated with the processor core supplies a copy of the target cache line to an upper level cache in the vertical cache hierarchy and retains a copy in a shared coherence state. The upper level cache holds the copy of the target cache line in a private shared ownership coherence state indicating that each cached copy of the target memory block is cached within the vertical cache hierarchy associated with the processor core. In response to the upper level cache signaling replacement of the copy of the target cache line in the private shared ownership coherence state, the lower level cache updates its copy of the target cache line to the exclusive ownership coherence state without coherency messaging with other vertical cache hierarchies.
摘要翻译：响应于针对目标高速缓存线的处理器核心的存储器访问请求，与处理器核心相关联的垂直高速缓存层级的较低级缓存将目标高速缓存行的副本提供给垂直高速缓存层级中的高级缓存并保留共享一致状态的副本。高级缓存将目标高速缓存行的副本保存在私有共享所有权一致状态中，指示目标存储器块的每个高速缓存副本被缓存在与处理器核心相关联的垂直高速缓存层级内。响应于在私有共享所有权相干状态下高级缓存信令替换目标高速缓存行的副本，下级缓存将其目标高速缓存行的副本更新为独占所有权相干状态，而不与其他垂直高速缓存的一致性消息传递层次结构。

49. 发明授权

US08683140B2 Cache-based speculation of stores following synchronizing operations 失效
标题翻译：同步操作后，存储器中基于缓存的推测
公开(公告)号：US08683140B2
公开(公告)日：2014-03-25
申请号：US13456420
申请日：2012-04-26
申请人： Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0837 , G06F12/0895
摘要： A method of processing store requests in a data processing system includes enqueuing a store request in a store queue of a cache memory of the data processing system. The store request identifies a target memory block by a target address and specifies store data. While the store request and a barrier request older than the store request are enqueued in the store queue, a read-claim machine of the cache memory is dispatched to acquire coherence ownership of target memory block of the store request. After coherence ownership of the target memory block is acquired and the barrier request has been retired from the store queue, a cache array of the cache memory is updated with the store data.
摘要翻译：在数据处理系统中处理存储请求的方法包括在数据处理系统的高速缓存存储器的存储队列中引入存储请求。存储请求通过目标地址识别目标存储器块并指定存储数据。当存储请求和存储请求之前的屏障请求在存储队列中排队时，调度高速缓冲存储器的读取机器以获取存储请求的目标存储器块的一致性所有权。在获取目标存储器块的一致性所有权并且屏障请求已经从存储队列中退出之后，用存储数据更新高速缓冲存储器的高速缓存阵列。

50. 发明授权

US08645627B2 Memory bus write prioritization 失效
标题翻译：内存总线写优先级
公开(公告)号：US08645627B2
公开(公告)日：2014-02-04
申请号：US13447462
申请日：2012-04-16
申请人： David M. Daly , Benjiman L. Goodman , Hillery C. Hunter , William J. Starke , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Hillery C. Hunter , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0888 , Y02D10/13
摘要： A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory controller includes a physical read queue that buffers data read from the system memory via the memory bus and a physical write queue that buffers data to be written to the system memory via the memory bus. The memory controller grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory.
摘要翻译：数据处理系统包括包括最低级高速缓存，耦合到多级高速缓存层级的处理器核心以及耦合到最低级高速缓存和存储器系统存储器的存储器总线的存储器控制器的多级高速缓存层级。存储器控制器包括物理读取队列，其缓冲通过存储器总线从系统存储器读取的数据，以及物理写入队列，其通过存储器总线缓冲要写入系统存储器的数据。存储器控制器基于最低级高速缓冲存储器中的多个脏高速缓存线，对存储器总线上的读操作授予优先级。

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