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41. 发明申请

US20110145802A1 ACCELERATING UNBOUNDED MEMORY TRANSACTIONS USING NESTED CACHE RESIDENT TRANSACTIONS 有权
标题翻译：使用嵌入式高速缓存交易来加速无关紧要的存储交易
公开(公告)号：US20110145802A1
公开(公告)日：2011-06-16
申请号：US12638103
申请日：2009-12-15
申请人： Yosseff Levanoni , Gad Sheaffer , Ali-Reza Adl-Tabatabai
发明人： Yosseff Levanoni , Gad Sheaffer , Ali-Reza Adl-Tabatabai
IPC分类号： G06F9/45 , G06F9/46 , G06F12/00 , G06F12/08
CPC分类号： G06F9/467
摘要： Using cache resident transaction hardware to accelerate a software transactional memory system. The method includes identifying a plurality of atomic operations intended to be performed by a software transactional memory system as transactional operations as part of a software transaction. The method further includes selecting at least a portion of the plurality of atomic operations. The method further includes attempting to perform the portion of the plurality of atomic operations as hardware transactions using cache resident transaction hardware.
摘要翻译：使用缓存驻留交易硬件来加速软件事务内存系统。该方法包括将期望由软件事务存储器系统执行的多个原子操作识别为作为软件事务的一部分的事务操作。该方法还包括选择多个原子操作的至少一部分。该方法还包括尝试使用高速缓存驻留交易硬件来执行多个原子操作的部分作为硬件事务。

42. 发明授权

US08539465B2 Accelerating unbounded memory transactions using nested cache resident transactions 有权
标题翻译：使用嵌套缓存常驻事务来加速无限制的内存事务
公开(公告)号：US08539465B2
公开(公告)日：2013-09-17
申请号：US12638103
申请日：2009-12-15
申请人： Yosseff Levanoni , Gad Sheaffer , Ali-Reza Adl-Tabatabai
发明人： Yosseff Levanoni , Gad Sheaffer , Ali-Reza Adl-Tabatabai
IPC分类号： G06F9/45
CPC分类号： G06F9/467
摘要： Using cache resident transaction hardware to accelerate a software transactional memory system. The method includes identifying a plurality of atomic operations intended to be performed by a software transactional memory system as transactional operations as part of a software transaction. The method further includes selecting at least a portion of the plurality of atomic operations. The method further includes attempting to perform the portion of the plurality of atomic operations as hardware transactions using cache resident transaction hardware.
摘要翻译：使用缓存驻留交易硬件来加速软件事务内存系统。该方法包括将期望由软件事务存储器系统执行的多个原子操作识别为作为软件事务的一部分的事务操作。该方法还包括选择多个原子操作的至少一部分。该方法还包括尝试使用高速缓存驻留交易硬件来执行多个原子操作的部分作为硬件事务。

43. 发明申请

US20140025901A1 TECHNIQUE FOR USING MEMORY ATTRIBUTES 有权
标题翻译：使用存储器属性的技术
公开(公告)号：US20140025901A1
公开(公告)日：2014-01-23
申请号：US14033463
申请日：2013-09-21
申请人： Quinn A. Jacobson , Anne C. Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham Chinya , Bratin Saha , Ali-Reza Adi-Tabatabai , Gad Sheaffer
发明人： Quinn A. Jacobson , Anne C. Bracy , Hong Wang , John P. Shen , Per Hammarlund , Matthew C. Merten , Suresh Srinivas , Kshitij A. Doshi , Gautham Chinya , Bratin Saha , Ali-Reza Adi-Tabatabai , Gad Sheaffer
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F11/3471 , G06F11/3648 , G06F12/0804 , G06F12/0817 , G06F12/0831 , G06F12/0842 , G06F12/145 , G06F2201/865
摘要： A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.
摘要翻译：使用存储器属性将信息中继到程序或其他代理的技术。更具体地，本发明的实施例涉及使用存储器属性位以有效的方式检查各种存储器特性。

44. 发明申请

US20160154742A1 DYNAMIC PINNING OF VIRTUAL PAGES SHARED BETWEEN DIFFERENT TYPE PROCESSORS OF A HETEROGENEOUS COMPUTING PLATFORM 有权
标题翻译：异步计算平台的不同类型处理器之间共享的虚拟页面动态拼接
公开(公告)号：US20160154742A1
公开(公告)日：2016-06-02
申请号：US14862745
申请日：2015-09-23
申请人： Gad Sheaffer , Boris Ginzburg , Ronny Ronen , Eliezer Weissmann
发明人： Gad Sheaffer , Boris Ginzburg , Ronny Ronen , Eliezer Weissmann
IPC分类号： G06F12/10 , G06F13/16
CPC分类号： G06F12/1027 , G06F12/0804 , G06F12/126 , G06F13/1663 , G06F2212/303 , G06F2212/657 , G06F2212/684
摘要： A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device, such as a graphics processing unit (GPU). The non-CPU may support virtual to physical address mapping and may thus be aware of the memory pages, which may not be pinned but may be accessed by the non-CPU. The non-CPU may notify or send such information to a run-time component such as a device driver associated with the CPU. The device driver may, dynamically, perform pinning of such memory pages, which may be accessed by the non-CPU. The device driver may even unpin the memory pages, which may be no longer accessed by the non-CPU. Such an approach may allow the memory pages, which may be no longer accessed by the non-CPU to be available for allocation to the other CPUs and/or non-CPUs.
摘要翻译：计算机系统可以支持一种或多种技术来允许由诸如图形处理单元（GPU）的非CPU设备访问的存储器页的动态固定。非CPU可以支持虚拟到物理地址映射，并且因此可以知道可能不被固定但可被非CPU访问的存储器页。非CPU可以向诸如与CPU相关联的设备驱动程序的运行时组件通知或发送这样的信息。设备驱动程序可以动态地执行可由非CPU访问的这种存储器页的钉扎。设备驱动程序甚至可以取消内存页，这可能不再被非CPU访问。这样的方法可以允许非CPU可以不再访问的存储器页面可用于分配给其他CPU和/或非CPU。

45. 发明授权

US09100938B2 Digital relay for out of network devices 有权
标题翻译：用于网络设备的数字继电器
公开(公告)号：US09100938B2
公开(公告)日：2015-08-04
申请号：US13817926
申请日：2012-05-09
申请人： Shmuel Ur , Gad Sheaffer
发明人： Shmuel Ur , Gad Sheaffer
IPC分类号： H04B7/14 , H04W4/00 , H04W76/02 , H04W88/04
CPC分类号： H04W76/02 , H04W76/10 , H04W88/04
摘要： In one example of digital relay for out of network devices, a communications device includes a detecting component configured to detect that one or more communication endpoints is within communication range, a message receiving component configured to receive a digital message from a first communication endpoint, and a message relaying component configured to transmit the digital message to the second communication endpoint, wherein the first communication endpoint and the second communication endpoint are not communicatively coupled to each other.
摘要翻译：在网络设备的数字中继的一个示例中，通信设备包括被配置为检测一个或多个通信端点在通信范围内的检测组件，被配置为从第一通信端点接收数字消息的消息接收组件，以及消息中继组件，被配置为将数字消息发送到第二通信端点，其中第一通信端点和第二通信端点不通信地彼此耦合。

46. 发明授权

US08341356B2 Protected cache architecture and secure programming paradigm to protect applications 有权
标题翻译：保护缓存架构和安全编程范例来保护应用程序
公开(公告)号：US08341356B2
公开(公告)日：2012-12-25
申请号：US13099479
申请日：2011-05-03
申请人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
发明人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
IPC分类号： G06F12/06
CPC分类号： G06F12/0802 , G06F12/0804 , G06F12/1491 , G06F21/10
摘要： Embodiments of the present invention provide a secure programming paradigm, and a protected cache that enable a processor to handle secret/private information while preventing, at the hardware level, malicious applications from accessing this information by circumventing the other protection mechanisms. A protected cache may be used as a building block to enhance the security of applications trying to create, manage and protect secure data. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供了一种安全编程范例和受保护的高速缓存，其使得处理器能够处理秘密/专用信息，同时防止恶意应用程序通过规避其他保护机制来访问该信息。受保护的缓存可以用作构建块，以增强试图创建，管理和保护安全数据的应用程序的安全性。描述和要求保护其他实施例。

47. 发明授权

US07975129B2 Selective hardware lock disabling 有权
标题翻译：选择性硬件锁定禁用
公开(公告)号：US07975129B2
公开(公告)日：2011-07-05
申请号：US12562457
申请日：2009-09-18
申请人： Shlomo Raikin , Gad Sheaffer , Doron Orenstlen
发明人： Shlomo Raikin , Gad Sheaffer , Doron Orenstlen
IPC分类号： G06F9/312
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/526
摘要： Controlling a reorder buffer (ROB) to selectively perform functional hardware lock disabling (HLD) is described. One apparatus embodiment includes a unit to enable an ROB to selectively disable a lock upon Identifying a lock acquire operation (LAO) associated with a critical section (CS) entry point, a unit to selectively retire the LAO, a unit to cause the ROB to selectively disable the lock, and a unit to snoop a buffer. The apparatus may, based on the snooping, selectively abort a transaction associated with the CS.
摘要翻译：描述了控制重排序缓冲器（ROB）以选择性地执行功能性硬件锁定禁止（HLD）。一个设备实施例包括一个单元，以使得ROB能够在识别与关键部分（CS）入口点相关联的锁定获取操作（LAO）时选择性地禁用锁定，该选择单元选择性地退出LAO，该单元使得ROB 选择性地禁用该锁，以及一个单元来窥探缓冲区。该设备可以基于窥探，选择性地中止与CS相关联的事务。

48. 发明申请

US20100169894A1 REGISTERING A USER-HANDLER IN HARDWARE FOR TRANSACTIONAL MEMORY EVENT HANDLING 有权
标题翻译：在硬件中注册用户处理事务处理事务处理
公开(公告)号：US20100169894A1
公开(公告)日：2010-07-01
申请号：US12346518
申请日：2008-12-30
申请人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin
发明人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin
IPC分类号： G06F9/46
CPC分类号： G06F9/466 , G06F9/528
摘要： A method and apparatus for registering a user-handler in hardware for transactional memory is herein described. A user-accessible register is to hold a reference to a transactional handler. An event register may also be provided to specify handler events, which may be done utilizing user-level software, privileged software, or by hardware. When an event is detected execution vectors to the transaction handler based on the reference to the transactional handler held in the user-accessible register. The transactional handler handles the event and then execution returns to normal flow.
摘要翻译：这里描述用于在用于事务存储器的硬件中注册用户处理程序的方法和装置。用户可访问的寄存器用于保存对事务处理程序的引用。还可以提供事件寄存器来指定处理程序事件，这可以使用用户级软件，特权软件或硬件来完成。当根据对用户可访问寄存器中保存的事务处理程序的引用检测事件到事务处理程序的执行向量时。事务处理程序处理事件，然后执行返回正常流程。

49. 发明授权

US07587584B2 Mechanism to exploit synchronization overhead to improve multithreaded performance 有权
标题翻译：利用同步开销来提高多线程性能的机制
公开(公告)号：US07587584B2
公开(公告)日：2009-09-08
申请号：US11070991
申请日：2005-03-02
申请人： Natalie D. Enright , Jamison D. Collins , Perry Wang , Hong Wang , Xinmin Tran , John Shen , Gad Sheaffer , Per Hammarlund
发明人： Natalie D. Enright , Jamison D. Collins , Perry Wang , Hong Wang , Xinmin Tran , John Shen , Gad Sheaffer , Per Hammarlund
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/4843 , G06F11/3419 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and an event detector to detect a long latency event associated with a synchronization object. The event detector can cause a first thread switch in response to the long latency event associated with the synchronization object. The apparatus may also include a spin detector to detect that the synchronization object is a contended synchronization object. The spin detector can cause a second thread switch in response to the detection of the contended synchronization object to enable a spin detect response.
摘要翻译：用于可激活其他线程的可编程事件驱动产量机制的方法，装置和程序装置。在一个实施例中，装置包括执行多个指令的执行资源和用于检测与同步对象相关联的长延迟事件的事件检测器。事件检测器可以响应于与同步对象相关联的长等待时间事件而导致第一线程切换。该装置还可以包括检测同步对象是竞争同步对象的自旋检测器。响应于竞争的同步对象的检测，自旋检测器可以引起第二线程切换以启用自旋检测响应。

50. 发明申请

US20090070774A1 LIVE LOCK FREE PRIORITY SCHEME FOR MEMORY TRANSACTIONS IN TRANSACTIONAL MEMORY 有权
标题翻译：实时锁定用于存储器交易的优先存储器
公开(公告)号：US20090070774A1
公开(公告)日：2009-03-12
申请号：US11854175
申请日：2007-09-12
申请人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
发明人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
IPC分类号： G06F9/46
CPC分类号： G06F9/524 , G06F9/466
摘要： A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value. When the FMV counter is at a predetermined number of aborts the counting logic is reset to avoid live lock.
摘要翻译：这里描述了用于在事务执行期间避免实时锁定的方法和装置。计数逻辑用于跟踪每个处理元素的成功提交事务。当在多个处理元件之间的事务之间检测到数据冲突时，以较低的计数逻辑值提供给处理元件的优先级。此外，如果值相同，则具有较低识别值的处理元件被赋予优先级，即允许在其他事务被中止时继续。为了避免在具有预定的计数逻辑值（例如最大计数值）的处理元件之间的实时锁定，当一个处理元件达到预定计数值时，所有计数器都被重置。此外，当计数逻辑处于最大值时，可以提供在最大值（FMV）计数器上的故障来计数事务的中止次数。当FMV计数器处于预定数量的中止时，计数逻辑被复位以避免实时锁定。

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