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    • 43. 发明授权
    • Charge storage for sensing operations in a DRAM
    • 充电存储用于DRAM中的感测操作
    • US5761112A
    • 1998-06-02
    • US717031
    • 1996-09-20
    • Michael A. MurrayLawrence C. LiuLi-Chun Li
    • Michael A. MurrayLawrence C. LiuLi-Chun Li
    • G11C7/06G11C7/10G11C11/24
    • G11C7/1048G11C7/065
    • A DRAM has a sensing circuit which includes an on-chip capacitors having a total capacitance greater than about 35% of the total capacitance of the bit lines. The on-chip capacitors are coupled to a power line of the sense amplifiers and stabilizes a power supply voltage to prevent voltage drop and noise during the large sensing currents for a read/refresh cycle. A read/refresh cycle in accordance with an embodiment of the invention includes precharging bit lines and the on-chip capacitors before connecting memory transistors to the bit lines and connecting power to the sense amplifiers. Capacitors can be formed in any available space in the integrated circuit particularly in space under metal bus lines in peripheral circuitry surrounding a memory array.
    • DRAM具有感测电路,该感测电路包括具有大于位线的总电容的约35%的总电容的片上电容器。 片上电容器耦合到读出放大器的电源线,并稳定电源电压,以防止在读/刷新周期的大感应电流期间的电压降和噪声。 根据本发明的实施例的读取/刷新周期包括在将存储器晶体管连接到位线之前预充电位线和片上电容器,并将功率连接到读出放大器。 电容器可以在集成电路的任何可用空间中形成,特别是在围绕存储器阵列的外围电路中的金属总线下方的空间中。
    • 50. 发明授权
    • DRAM with new I/O data path configuration
    • DRAM具有新的I / O数据路径配置
    • US5781488A
    • 1998-07-14
    • US844541
    • 1997-04-18
    • Lawrence C. LiuMichael A. MurrayLi-Chun Li
    • Lawrence C. LiuMichael A. MurrayLi-Chun Li
    • G11C7/10G11C11/4096G11C7/02
    • G11C11/4096G11C7/1048G11C7/1051
    • In accordance with this invention, a DRAM with a staggered bitline sense amplifier configuration utilizes an I/O data path scheme which minimizes the time delay through the I/O data path. The DRAM includes a first and a second memory arrays wherein a first external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected from the first memory array via a first column decoding circuit. A second external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected form the second memory array via a second column decoding circuit. Each of the two external sense amplifiers has an output terminal which are shorted together. A tristate signal feeding another input terminal of each of the two external sense amplifiers is used to eliminate data contention on the shorted output terminals.
    • 根据本发明,具有交错位线读出放大器配置的DRAM利用I / O数据路径方案,其使通过I / O数据路径的时间延迟最小化。 DRAM包括第一和第二存储器阵列,其中第一外部读出放大器经由第一列解码电路在输入端子上接收对应于从第一存储器阵列选择的存储器单元的状态的信号。 第二外部读出放大器经由第二列解码电路在输入端子上接收对应于从第二存储器阵列选择的存储器单元的状态的信号。 两个外部读出放大器中的每一个具有一起短接的输出端子。 使用两个外部读出放大器中的每一个的另一个输入端子的三态信号来消除短路输出端子上的数据争用。