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    • 46. 发明授权
    • Method and configuration for connecting test structures or line arrays for monitoring integrated circuit manufacturing
    • 用于连接用于监控集成电路制造的测试结构或线阵列的方法和配置
    • US08178876B2
    • 2012-05-15
    • US10595384
    • 2004-04-30
    • Christopher HessDavid Goldman
    • Christopher HessDavid Goldman
    • H01L23/58
    • H01L22/34G01R31/2884H01L2924/0002H01L2924/3011H01L2924/00
    • A test chip comprises at least one level having an array of regions. Each region is capable of including at least one test structure. At least some of the regions include respective test structures. The level has a plurality of driver lines that provide input signals to the test structures. The level has a plurality of receiver lines that receive output signals from the test structures. The level has a plurality of devices for controlling current flow. Each test structure is connected to at least one of the driver lines with a first one of the devices in between. Each test structure is connected to at least one of the receiver lines with a second one of the devices in between, so that each of the test structures can be individually addressed for testing using the driver lines and receiver lines.
    • 测试芯片包括具有区域阵列的至少一个级别。 每个区域能够包括至少一个测试结构。 至少一些区域包括相应的测试结构。 电平具有多个驱动线,其向测试结构提供输入信号。 电平具有接收来自测试结构的输出信号的多个接收线。 该电平具有用于控制电流的多个装置。 每个测试结构都与至少一个驱动器线连接,其中的第一个设备之间。 每个测试结构与至少一个接收器线路连接,其间具有第二个设备,使得每个测试结构可以被单独寻址,以便使用驱动器线路和接收器线路进行测试。