专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US06906939B2 Re-writable memory with multiple memory layers 有权
公开(公告)号：US06906939B2
公开(公告)日：2005-06-14
申请号：US10612191
申请日：2003-07-01
申请人： Darrell Rinerson , Christophe J. Chevallier , Steven W. Longcor , Wayne Kinney , Edmond R. Ward
发明人： Darrell Rinerson , Christophe J. Chevallier , Steven W. Longcor , Wayne Kinney , Edmond R. Ward
IPC分类号： G11C11/56 , G11C13/00 , G11C16/02 , H01L27/24 , G11C5/06
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C2213/31
摘要： A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminals selected. Sharing logic over multiple layers allows driver sets to be reused.

42. 发明授权

US06870755B2 Re-writable memory with non-linear memory element 失效
标题翻译：具有非线性存储元件的可重写存储器
公开(公告)号：US06870755B2
公开(公告)日：2005-03-22
申请号：US10604556
申请日：2003-07-30
申请人： Darrell Rinerson , Christophe J. Chevallier , Steven W. Longcor , Wayne Kinney , Edmond R. Ward , Steve Kuo-Ren Hsia
发明人： Darrell Rinerson , Christophe J. Chevallier , Steven W. Longcor , Wayne Kinney , Edmond R. Ward , Steve Kuo-Ren Hsia
IPC分类号： G11C13/00 , G11C11/00
CPC分类号： G11C13/0007 , G11C13/003 , G11C2213/31 , G11C2213/72 , G11C2213/74 , G11C2213/77
摘要： A re-writable memory that uses resistive memory cell elements with non-linear IV characteristics is disclosed. Non-linearity is important in certain memory arrays to prevent unselected cells from being disturbed and to reduce the required current. Non-linearity refers to the ability of the element to block the majority of current up to a certain level, but then, once that level is reached, the element allows the majority of the current over and above that level to flow.
摘要翻译：公开了一种使用具有非线性IV特性的电阻性存储单元元件的可重写存储器。在某些存储器阵列中非线性是重要的，以防止未选择的单元被干扰并减少所需的电流。非线性是指元件将大多数电流阻塞到一定水平的能力，但是，一旦达到该电平，该元件允许超过该电平的大部分电流流动。

43. 发明授权

US06753561B1 Cross point memory array using multiple thin films 有权
标题翻译：使用多个薄膜的交叉点存储阵列
公开(公告)号：US06753561B1
公开(公告)日：2004-06-22
申请号：US10330512
申请日：2002-12-26
申请人： Darrell Rinerson , Steven W. Longcor , Edmond R. Ward , Steve Kuo-Ren Hsia , Wayne Kinney , Christophe J. Chevallier
发明人： Darrell Rinerson , Steven W. Longcor , Edmond R. Ward , Steve Kuo-Ren Hsia , Wayne Kinney , Christophe J. Chevallier
IPC分类号： H01L31062
CPC分类号： H01L27/2418 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C2213/31 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/165
摘要： Cross point memory array using multiple thin films. The invention is a cross point memory array that uses conductive array lines and multiple thin films as a memory plug. The thin films of the memory plug include a memory element and a non-ohmic device. The memory element switches between resistive states upon application of voltage pulses and the non-ohmic device imparts a relatively high resistance to the memory plug upon application of low magnitude voltages.
摘要翻译：使用多个薄膜的交叉点存储阵列。本发明是使用导电阵列线和多个薄膜作为存储器插头的交叉点存储器阵列。存储器插头的薄膜包括存储器元件和非欧姆器件。存储器元件在施加电压脉冲时在电阻状态之间切换，并且非欧姆器件在施加低幅度电压时对存储器插头施加相当高的电阻。

44. 发明授权

US5973374A Flash memory array having well contact structures 失效
标题翻译：具有良好接触结构的闪存阵列
公开(公告)号：US5973374A
公开(公告)日：1999-10-26
申请号：US938420
申请日：1997-09-25
申请人： Steven W. Longcor
发明人： Steven W. Longcor
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/115 , H01L27/11521
摘要： A common source flash memory array providing multiple well contact structures distributed within the array without the need for separate well tap regions connected to dedicated channel lines. The contact locations between Vss metal common source lines and source bus regions are used to provide additional contacts between Vss metal lines and p+ well taps, all of the source bus regions and the p+ well tap regions being encompassed within a double-well configuration. Depending on the specific embodiment of the present invention, the n+ diffused source bus regions and the nearby p+ well tap may: (a) be separately tied to the Vss metal common source line through separate contact metals (e.g., tungsten plugs); (b) be butted against each other and tied to a common Vss metal source line through separate contact metals; (c) be butted against each other and tied to a common Vss metal source line through a common contact metal (e.g., an enlarged plug) overlapping both the n+ diffused source bus regions and the p+ well tap; or (d) be tied to a common Vss metal source line through a common contact metal and a metal silicide layer.
摘要翻译：提供分布在阵列内的多个阱接触结构的公共源闪存阵列，而不需要连接到专用信道线的单独的阱抽头区域。 Vss金属公共源极线和源极总线区之间的接触位置用于在Vss金属线和p +阱分接头之间提供附加接触，所有源极总线区域和p +阱分接区域都包含在双阱配置中。根据本发明的具体实施例，n +扩散源极总线区域和附近的p +阱分接头可以：（a）通过单独的接触金属（例如钨插塞）分开地连接到Vss金属公共源极线; （b）通过单独的接触金属对接并与普通Vss金属源线连接; （c）通过与n +扩散的源极总线区域和p +阱分接头重叠的公共接触金属（例如，扩大的插塞）彼此对接并连接到公共的Vss金属源极线; 或（d）通过公共接触金属和金属硅化物层与公共Vss金属源极线连接。

45. 发明授权

US07884349B2 Selection device for re-writable memory 有权
标题翻译：可重写存储器的选择装置
公开(公告)号：US07884349B2
公开(公告)日：2011-02-08
申请号：US12283339
申请日：2008-09-11
申请人： Darrell Rinerson , Steve Kuo-Ren Hsia , Steven W. Longcor , Wayne Kinney , Edmond Ward , Christophe J. Chevallier
发明人： Darrell Rinerson , Steve Kuo-Ren Hsia , Steven W. Longcor , Wayne Kinney , Edmond Ward , Christophe J. Chevallier
IPC分类号： H01L29/06
CPC分类号： H01L27/101 , G11C11/00 , G11C11/56 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C2213/31 , G11C2213/72 , G11C2213/74 , G11C2213/77 , G11C2213/79 , H01L27/11502 , H01L27/11507 , H01L27/24 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/00 , H01L45/10 , H01L45/1233 , H01L45/147
摘要： A memory cell including a memory element and a non-ohmic device (NOD) that are electrically in series with each other is disclosed. The NOD comprises a semiconductor based selection device operative to electrically isolate the memory element from a range of voltages applied across the memory cell that are not read voltages operative read stored data from the memory element or write voltages operative to write data to the memory element. The selection device may comprise a pair of diodes that are electrically in series with each other and disposed in a back-to-back configuration. The memory cell may be fabricated over a substrate (e.g., a silicon wafer) that includes active circuitry. The selection device and the semiconductor materials (e.g., poly-silicon) that form the selection device are fabricated above the substrate and are integrated with other thin film layers of material that form the memory cell.
摘要翻译：公开了一种包括彼此电串联的存储元件和非欧姆器件（NOD）的存储单元。 NOD包括基于半导体的选择装置，其操作以将存储器元件与施加在存储器单元上的电压范围电隔离，所述电压范围不是读取电压，从存储元件读取存储的数据，或者写入电压可操作以将数据写入存储器元件。选择装置可以包括彼此电连接并以背对背配置设置的一对二极管。可以在包括有源电路的衬底（例如，硅晶片）上制造存储器单元。形成选择装置的选择装置和半导体材料（例如，多晶硅）制造在衬底之上，并与形成存储单元的材料的其它薄膜层集成。

46. 发明申请

US20100159641A1 Memory cell formation using ion implant isolated conductive metal oxide 失效
标题翻译：使用离子注入隔离导电金属氧化物的存储单元形成
公开(公告)号：US20100159641A1
公开(公告)日：2010-06-24
申请号：US12653851
申请日：2009-12-18
申请人： Darrell Rinerson , Jonathan Bornstein , David Hansen , Robin Cheung , Steven W. Longcor , Rene Meyer , Lawrence Schloss
发明人： Darrell Rinerson , Jonathan Bornstein , David Hansen , Robin Cheung , Steven W. Longcor , Rene Meyer , Lawrence Schloss
IPC分类号： H01L21/34
CPC分类号： F01D17/26 , F04D29/563 , H01L21/02565 , H01L27/0688 , H01L27/2409 , H01L27/2418 , H01L27/2472 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1666
摘要： Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).
摘要翻译：公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOX，LaSrCoOX，LaNiOX等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触，并且形成用于将非易失性数据存储为多个的存储元件（例如，表示存储数据的电阻状态）。

47. 发明授权

US07439082B2 Conductive memory stack with non-uniform width 有权
标题翻译：具有不均匀宽度的导电存储器堆叠
公开(公告)号：US07439082B2
公开(公告)日：2008-10-21
申请号：US11369663
申请日：2006-03-06
申请人： Darrell Rinerson , Steven W. Longcor , Steve Kuo-Ren Hsia
发明人： Darrell Rinerson , Steven W. Longcor , Steve Kuo-Ren Hsia
IPC分类号： H01L21/8242
CPC分类号： G11C13/0007 , G11C11/5685 , G11C2213/31 , H01L27/11502 , H01L27/11507 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element that is sandwiched between the electrodes. The bottom electrode can be described as having a top face with a first surface area, the top electrode has a bottom face with a second surface area and the multi-resistive state element has a bottom face with a third surface area and a top face with a fourth surface area. The multi-resistive state element's bottom face is in contact with the bottom electrode's top face and the multi-resistive state element's top face is in contact with the top electrode's bottom face. Furthermore, the fourth surface area is not equal to the second surface area.
摘要翻译：提供导电存储器堆叠。存储器堆叠包括底电极，顶电极和夹在电极之间的多电阻状态元件。底电极可以被描述为具有第一表面区域的顶面，顶电极具有具有第二表面区域的底面，并且多电阻状态元件具有带有第三表面区域的底面和顶面第四表面积。多电阻状态元件的底面与底部电极的顶面接触，并且多电阻状态元件的顶面与顶部电极的底面接触。此外，第四表面积不等于第二表面积。

48. 发明授权

US07382644B2 Two terminal memory array having reference cells 有权
公开(公告)号：US07382644B2
公开(公告)日：2008-06-03
申请号：US11725045
申请日：2007-03-16
申请人： Darrell Rinerson , Christophe J. Chevallier , Steven W. Longcor
发明人： Darrell Rinerson , Christophe J. Chevallier , Steven W. Longcor
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2213/31 , G11C2213/71 , G11C2213/77
摘要： A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.

49. 发明授权

US07095643B2 Re-writable memory with multiple memory layers 有权
标题翻译：具有多个内存层的可重写内存
公开(公告)号：US07095643B2
公开(公告)日：2006-08-22
申请号：US11151880
申请日：2005-06-13
申请人： Darrell Rinerson , Christophe Chevallier , Wayne Kinney , Steven W. Longcor , Edmond R. Ward
发明人： Darrell Rinerson , Christophe Chevallier , Wayne Kinney , Steven W. Longcor , Edmond R. Ward
IPC分类号： G11C5/06
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C2213/31
摘要： A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminals selected. Sharing logic over multiple layers allows driver sets to be reused.
摘要翻译：具有多个内存层的可重写内存。只要存在只有一个选择了两个端子的存储单元，就可以选择使用层叠交叉点结构中的存储单元的两个端子进行选择，以便选择多层导电线。通过多层共享逻辑可以重新使用驱动程序集。

50. 发明授权

US07079442B2 Layout of driver sets in a cross point memory array 有权
标题翻译：驱动程序集在交叉点存储器阵列中的布局
公开(公告)号：US07079442B2
公开(公告)日：2006-07-18
申请号：US10612733
申请日：2003-07-01
申请人： Darrell Rinerson , Christophe J. Chevallier , Steven W. Longcor , Wayne Kinney , Edmond R. Ward
发明人： Darrell Rinerson , Christophe J. Chevallier , Steven W. Longcor , Wayne Kinney , Edmond R. Ward
IPC分类号： G11C7/00
CPC分类号： G11C5/025 , G11C11/16 , G11C11/5685 , G11C13/0007 , G11C2213/31
摘要： Layouts of driver sets in a cross point memory array. Since both terminals of a memory cell in a cross point structure are typically used for selection purposes, dedicated driver sets are typically required for both x and y directions. By fabricating the cross point array above the driver circuitry, several different driver set layouts can be utilized that allow for varying designs.
摘要翻译：在交叉点存储器阵列中布置驱动程序集。由于交叉点结构中的存储单元的两个端子通常用于选择目的，所以通常对于x和y方向都需要专用的驱动器组。通过在驱动器电路上方制造交叉点阵列，可以利用允许不同设计的几种不同的驱动器组布局。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式